View ADE3700SX_461527.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ADE3700
Analog LCD Display Engine for XGA and SXGA Resolutions
TARGET SPECIFICATION
Feature Overview
s Programmable Context SensitiveTM Scaling s High-quality Up-scaling and Down-scaling s Integrated 9-bit ADC/PLL s IQSyncTM AutoSetup s Integrated programmable Timing Controller s Integrated Pattern Generator s Perfect PictureTM Technology s sRGB 3D Color Warp s Integrated OSD s Advanced EMI reduction features s Framelock operation with Safety ModeTM s Serial IC interface s Low power 0.18 m process technology
General Description
ADE3700 devices are a family of highly-integrated display engine ICs, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for analog-only input LCD display applications. The ADE3700 covers the full range of XGA and SXGA analog-only applications including Smart Panel designs. The ADE3700 family is pin-to-pin compatible and comes in a low-cost, 128-pin LQFP package. ADE3700 devices use the same software platform and are backward-compatible with the previous generation of ADE3xxx Scaling Engines.
Microcontroller IC Line-Lock PLL On-Screen Display Engine
Firmware ROM
Pattern Generator
Analog RGB Video Signals
Triple 9-bit ADC Fast and accurate adjustments of: *Phase *Position *Level *Clock
Interlace Mode Detection IQ ScalingTM Engine with Context SensitiveTM Filtering
EMI Reduction * Per Pin Delay * Slew Rate Control * Spread Spectrum * Data Inversion
ADE 3700
Programmable Timing Controller (TCON)
30-bit Programmable Gamma Table
RSDS LVCMOS Programmable Output Formatter
To TFT LCD Panel
sRGB 3D Color Warp Temporal & Spatial Dithering
LCD Scaler Product Selector
Output Format Support Product Package Resolution
ADE3700X ADE3700XT ADE3700SX 128 LQFP 128 LQFP 128 LQFP Up to XGA 75 Hz Up to XGA 75 Hz Up to SXGA 75 Hz Yes
Input Interface Support Analog
Yes Yes Yes
TCON
DVI
YUV
October 2003
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
1/89
ADE3700
Third Generation Context SensitiveTM Scaler
q q
OSD Engine
q q q
Sharper text with Edge Enhancement RAM based coefficients for unique customization 5:1 Upscale and 2:1 Downscale Independent X - Y axis zoom and shrink
256 RAM based 12x18 characters 1- and 4-bit per pixel color characters Bordering, shadowing, transparency, fade-in, and fade-out effects Supports font rotation Up to 4 sub windows 32-entry TrueColor LUT
q q
q q q
Analog RGB input
q q q
140 MHz 9-bit ADC Ultra low jitter digital Line Lock PLL Composite Sync and Sync on Green support
Programmable Timing Controller (TCON)
q
IQsyncTM AutoSetup
q
Highly programmable support for XGA SmartPanels Dual-function LVCMOS and RSDS outputs Supports 18-, 24-, 36-, and 48-bit RSDS outputs Advanced Flicker Detection and Reduction 12 programmable timing signals for row/ column control Wide range of drivers & TCON compatibility Simulation tools for easy programming Supports complex polarity generation for IPS panels
AutoSetup configures phase, clock, level, and position Supports continuous calibration for reduced user intervention Automatically detects activity on input Compatible with all standard VESA and GTF modes
q q
q
q q
q q
q q q
Perfect PictureTM Technology
q q
Programmable 3D Color Warp Digital brightness, contrast, hue, and saturation gamma controls for all inputs Simple white point control Compatible with sRGB standard Video & Picture windowing Supports up to 7 different windows Independent window controls for contrast brightness, saturation, hue and gamma
Advanced EMI Reduction Features
q
q q q q q
Flexible data inversion / transition minimization, single, dual, and separate Per pin delay, 0 to 6ns in 0.4ns increments Adaptive Slew Rate control outputs Differential clock Spread spectrum -programmable digital FM modulation of the output clock with no external components
q q q q
Perfect ColorTM Technology
q q q
True color dithering for 12- and 18-bit panels Temporal and spatial dithering 30-bit programmable gamma table
Output Format
q q q
Supports resolutions up to SXGA @ 75Hz Supports 6- or 8-bit Panels Supports double or single pixel wide formats
2/89
ADE3700
Table of Contents
Chapter 1
1.1
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Descriptions .................................................................................................................. 7
Chapter 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Global Control .................................................................................................................... 11 FM Frequency Synthesizer ................................................................................................ 16 Analog-to-Digital Converter (ADC) ..................................................................................... 17 Line Lock PLL .................................................................................................................... 18 Sync Retiming (SRT) ......................................................................................................... 23 Sync Measurement ............................................................................................................ 25 Sync Multiplexer (SMUX) ................................................................................................... 32
2.7.1 2.7.2 Functional Description .......................................................................................................................33 Example .............................................................................................................................................34
2.8 2.9
Data Multiplexer ................................................................................................................. 37 Data Measurement (DMEAS) ............................................................................................ 38
2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 2.9.6 2.9.7 Edge Intensity ....................................................................................................................................38 Pixel Sum ...........................................................................................................................................38 Minimum/Maximum Pixel ...................................................................................................................38 Pixel Cumulative Distribution (PCD) ..................................................................................................39 Horizontal Position .............................................................................................................................39 Vertical Position .................................................................................................................................39 DE Size ..............................................................................................................................................40
2.10 2.11
LCD Scaler ......................................................................................................................... 42 Output Sequencer .............................................................................................................. 45
2.11.1 2.11.2 2.11.3 Frame Synchronization ......................................................................................................................45 Timing Unit .........................................................................................................................................45 Signal Generation ..............................................................................................................................45
2.12 2.13
Timing Controller (TCON) .................................................................................................. 48 Pattern Generator .............................................................................................................. 54
2.13.1 2.13.2 2.13.3 Screen Split .......................................................................................................................................54 Pattern Engine ...................................................................................................................................55 Borders ..............................................................................................................................................55
2.14
sRGB .................................................................................................................................. 60
2.14.1 2.14.2 Parametric Gamma, Digital Contrast / Brightness on Multiple Windows ...........................................60 Color Space Warp ..............................................................................................................................60
2.15 2.16
On-Screen Display (OSD) .................................................................................................. 62
2.15.1 OSD Access via I2C ..........................................................................................................................62
Flicker ................................................................................................................................. 68
3/89
ADE3700
2.17 2.18 2.19 Gamma ...............................................................................................................................70 APC ....................................................................................................................................71 Output Multiplexer ..............................................................................................................72
2.19.1 2.19.2 2.19.3 Sub Block Function ........................................................................................................................... 73 RSDS ................................................................................................................................................ 76 Per Pin Delay .................................................................................................................................... 77
2.20 2.21 2.22
Pulse Width Modulation (PWM) ..........................................................................................80 DFT Block ...........................................................................................................................81 IC RAM Addresses ...........................................................................................................83
Chapter 3
3.1 3.2 3.3 3.4 3.5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Absolute Maximum Ratings ................................................................................................84 Power Consumption Matrices .............................................................................................84 Nominal Operating Conditions ............................................................................................85 Preliminary Thermal Data ...................................................................................................85 Preliminary DC Specifications ............................................................................................85
3.5.1 3.5.2 3.5.3 3.5.4 LVTTL 5 Volt Tolerant Inputs With Hysteresis ................................................................................... 85 LVTTL 5 Volt Tolerant Inputs ............................................................................................................. 85 LVTTL 5 Volt Tolerant I/O With Hysteresis ........................................................................................ 86 LVTTL Outputs .................................................................................................................................. 86
3.6
Preliminary AC Specifications ...........................................................................................86
Chapter 4 Chapter 5
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4/89
ADE3700
1
General Information
The ADE3700 family of devices is capable of implementing all of the advanced features of today's LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for controlling the ADE3700 and other monitor functions.
Figure 1: ADE3700 Block Diagram
DATA CTRL DMEAS Timing Controller Output Format Color Management OSD SMEAS SCLK Frequency Synthesizer SCLK Pattern Generator DOTCLK FM Freq. Synthesizer GAMMA LUT Blocks Used
GLBL SMEAS LLK ADC OSD SCALER GAMMA SRGB OUTSEQ TCON APC OMUX SMEAS
Analog Port
LCD Scaler
LLKPLL
INCLK
The ADE3700 architecture unburdens the MCU from all data-intensive pixel manipulations, providing an optimal blend of features and code customizing without incurring the cost of a 16-bit processor or memory. The key interactions between the monitor MCU and the ADE3700 can be broken down into the features shown in the table below.
Table 1: ADE3700 Features (Sheet 1 of 2) Feature
Power-up / Initialize
Description of ADE3700 Operation
When power is first applied, the ADE3700 is asynchronously reset from a pin. The MCU typically programs the ADE3700 with a number of default values and sets up the ADE3700 to identify activity on any of the input pins. All preconfigured values and RAMs, such as DVI settings, line-lock PLL settings, OSD characters, LCD timing values (output sequencer), scale kernels, gamma curves, sRGB color warp, APC dithering, output pin configuration (OMUX), etc. can be pre-loaded into the ADE3700. The typical end state is that the ADE3700 is initialized into a low power mode, ready to turn active once the power button is pressed.
Pages
11 25 18 17 62 42 70 60 45 48 71 72 25
Activity Detect
When the monitor has been powered on, the inputs can be monitored for active video sources. Based on the activity monitors, the MCU chooses an input or power down state.
5/89
ADE3700
Table 1: ADE3700 Features (Sheet 2 of 2) Feature
Sync / Timing Measurement Mode Set
Description of ADE3700 Operation
Once an input source is selected, all available information on frequencies and line/pixel counts is measured for the selected source and made available to the MCU. Once the MCU has determined the matching video mode or calculated a video mode using a GTF algorithm, the datapath is programmed to drive the flat panel. Clock frequencies for the internal memory and datapath are also set at this time.
Blocks Used
SMEAS
Pages
25
GLBL LLK SRT DMUX SMUX SCALER DMEAS LLK ADC SMUX SRT SRGB SRGB GAMMA SRGB PGEN FLICKER TCON PWM
11 18 23 37 32 42 47 18 17 32 23 60 60 70 60 54 68 48 80
Autotune
When the MCU calls for an autotune, the MCU sets up an iterative loop to search for the best phase, gain, offset, etc. At each step of the loop, the MCU kicks off a test in which the ADE3700 which performs extensive statistical analysis of the incoming data stream. The results of the analysis are made available to the MCU which is responsible for the optimization algorithm. In response to user OSD control, the MCU can program single 8-bit registers that set brightness and contrast for each color channel independently. In response to user OSD control, the MCU can program three 8-bit registers that set the white point for the output. The MCU can program the gamma RAMs to implement 10-bit accurate color transformations. The SRGB block allows simple, intuitive color control with just a few registers. For production testing, the ADE3700 can be programmed by the MCU to output a wide set of test patterns. For Smart Panel applications, the MCU can set up the flicker detection block to report any correlation with the polarity inversion signal. The MCU can then change the polarity inversion to a non-correlating pattern to eliminate flicker. The ADE3700 provides two PWM outputs for direct control of the power components in a typical backlight. The MCU sets up the registers and enables the function. To enter a low power state, the MCU can gate of most of the clocks and put the analog blocks into a low power standby state.
Digital Contrast / Brightness White Point Control GAMMA Adjustment sRGB Control Pattern Generation Flicker Reduction
Backlight Control
Low Power State
GLBL
11
6/89
ADE3700
Pin Descriptions
1.1
Pin Descriptions
Table 2: Pinout (Sheet 1 of 4)
LQFP128
32 31 30 29 19 18 34 21 65 8 9 10 11 12 13 14 15 17 16 20 54 55 48 41 47 58 51 44 40 26 28 25 27 105 126 127
Name
XVDD18 XTAL_OUT XTAL_IN XGND XCLK_EN XCLK VSYNC TSTCLK TST_SCAN TCON7 TCON6/OVS TCON5/OHS TCON4/ODE TCON3 TCON2 TCON1 TCON0 SDA SCL RESETN REFR REFMR REFMG REFMB REFG REFCR REFCG REFCB REFB PVDD18 PVDD18 PGND PGND AVS ORB7 ORB6
Type
Power Output Input Power Input Output Input Input Input Output Output Output Output Input/Output Input/Output Input/Output Input/Output Open Drain I/O Input Input Passive Passive Passive Passive Passive Passive Passive Passive Passive Power Power Power Power Output Input/Output Input/Output Crystal Oscillator 1.8V VDD Crystal Oscillator output Crystal Oscillator input Crystal Oscillator Ground Crystal clock output enable
Description
Crystal clock buffered output Vertical Sync Input Connect to Digital Ground Connect to Digital Ground TCON Output 7 TCON Output 6/Output Vertical Sync TCON Output 5/Output Horizontal Sync TCON Output 4/Output Data Enable TCON Output 3 TCON Output 2 TCON Output 1 TCON Output 0 I2C Data I2C Clock Reset input, Active Low 1% 15.0 kOhm resistor to Analog Ground Connect to Analog Ground Connect to Analog Ground Connect to Analog Ground 1% 15.0 kOhm resistor to Analog Ground 100nF capacitor to Analog Ground 100nF capacitor to Analog Ground 100nF capacitor to Analog Ground 1% 15.0 kOhm resistor to Analog Ground PLL 1.8V VDD PLL 1.8V VDD PLL Ground PLL Ground Alternate Vertical Sync Output Port B: Red Data 7 Output Port B: Red Data 6
7/89
Pin Descriptions
Table 2: Pinout (Sheet 2 of 4) LQFP128
128 1 2 3 4 5 86 87 88 89 90 95 96 97 103 112 113 114 115 120 121 122 123 74 75 76 77 78 79 82 83 102 104 98 99 100 101 ORB5 ORB4 ORB3 ORB2 ORB1 ORB0 ORA7 ORA6 ORA5 ORA4 ORA3 ORA2 ORA1 ORA0 AHS OGB7 OGB6 OGB5 OGB4 OGB3 OGB2 OGB1 OGB0 OGA7 OGA6 OGA5 OGA4 OGA3 OGA2 OGA1 OGA0 ADE OCLK OBB7 OBB6 OBB5 OBB4
ADE3700
Name
Type
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output Input/Output Input/Output Input/Output Input/Output Output Port B: Red Data 5 Output Port B: Red Data 4 Output Port B: Red Data 3 Output Port B: Red Data 2 Output Port B: Red Data 1 Output Port B: Red Data 0 Output Port A: Red Data 7 Output Port A: Red Data 6 Output Port A: Red Data 5 Output Port A: Red Data 4 Output Port A: Red Data 3 Output Port A: Red Data 2 Output Port A: Red Data 1 Output Port A: Red Data 0 Alternate Horizontal Sync
Description
Output Port B: Green Data 7 Output Port B: Green Data 6 Output Port B: Green Data 5 Output Port B: Green Data 4 Output Port B: Green Data 3 Output Port B: Green Data 2 Output Port B: Green Data 1 Output Port B: Green Data 0 Output Port A: Green Data 7 Output Port A: Green Data 6 Output Port A: Green Data 5 Output Port A: Green Data 4 Output Port A: Green Data 3 Output Port A: Green Data 2 Output Port A: Green Data 1 Output Port A: Green Data 0 Alternate Data Enable Output Clock Output Port B: Blue Data 7 Output Port B: Blue Data 6 Output Port B: Blue Data 5 Output Port B: Blue Data 4
8/89
ADE3700
Table 2: Pinout (Sheet 3 of 4) LQFP128
108 109 110 111 66 67 68 69 70 71 72 73 56 49 42 35 7 64 80 91 106 119 23 62 84 93 117 124 6 22 24 63 81 85 92 94 107 OBB3 OBB2 OBB1 OBB0 OBA7 OBA6 OBA5 OBA4 OBA3 OBA2 OBA1 OBA0 INR ING INB HSYNC DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DGND DGND DGND DGND DGND DGND DGND DGND DGND
Pin Descriptions
Name
Type
Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Input Input Input Input Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Output Port B: Blue Data 3 Output Port B: Blue Data 2 Output Port B: Blue Data 1 Output Port B: Blue Data 0 Output Port A: Blue Data 7 Output Port A: Blue Data 6 Output Port A: Blue Data 5 Output Port A: Blue Data 4 Output Port A: Blue Data 3 Output Port A: Blue Data 2 Output Port A: Blue Data 1 Output Port A: Blue Data 0
Description
Analog Video Port: Red Channel input Analog Video Port: Green Channel input Analog Video Port: Blue Channel input Horizontal (or Composite) Sync Input Digital 3.3V VDD Digital 3.3V VDD Digital 3.3V VDD Digital 3.3V VDD Digital 3.3V VDD Digital 3.3V VDD Digital 1.8V VDD Digital 1.8V VDD Digital 1.8V VDD Digital 1.8V VDD Digital 1.8V VDD Digital 1.8V VDD Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground
9/89
Pin Descriptions
Table 2: Pinout (Sheet 4 of 4) LQFP128
116 118 125 33 36 43 50 57 46 53 60 37 39 45 52 59 61 38 DGND DGND DGND CSYNC AVDD33 AVDD33 AVDD33 AVDD33 AVDD18 AVDD18 AVDD18 AGND AGND AGND AGND AGND AGND ADVDD18
ADE3700
Name
Type
Power Power Power Input Power Power Power Power Power Power Power Power Power Power Power Power Power Power Digital Ground Digital Ground Digital Ground
Description
Composite Sync Input - for Sync On Green Analog 3.3V VDD Analog 3.3V VDD Analog 3.3V VDD Analog 3.3V VDD Analog 1.8V VDD Analog 1.8V VDD Analog 1.8V VDD Analog Ground Analog Ground Analog Ground Analog Ground Analog Ground Analog Ground 1.8V VDD
10/89
ADE3700
Global Control
2
2.1
Functional Description
Global Control
The global control block is responsible for:
q q q q q
selecting clock sources power control IC control SCLK frequency synthesizer control block by block synchronous reset generation
The global control block runs on the XCLK clock domain which is required to be active for programming. The clock domains of all other blocks are set in the Global Control Block. For IC access, the requested block must be driven with a valid clock frequency greater than 10 MHz. Clock domains are shown in Figure 2.
Figure 2: Global Control Block Diagram MCU (SCL, SDA)
IC Global
PWM
Sync Measure Sync Re-Time Pattern Generator GAMMA
ADE3700
XCLK Domain
Flicker Detection
PC Analog
INR, G, B V, H, Csync
ADC (Analog) ADC Digital I/F
Data
sRGB
OSD
Output Multiplexer
LCD Scaler
APC
ORA OGA OBA ORB OGB OBB OCLK ODE OHS OVS TCON
Line Lock PLL
Data Measure
SCLK Domain INCLK Domain
SCLK Freq. Synthesizer
Output Sequencer TCON
DOTCLK Domain
FM Freq. Synthesizer
To program the SCLK frequency synthesizer to a desired frequency (fOUT, in MHz), the following equations apply.
Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 1 of 2) Frequency Range
fOUT < 8 x fXCLK AND fOUT 4 x fXCLK fOUT < 4 x fXCLK AND fOUT 2 x fXCLK
SDIV
0 1
11/89
Global Control
Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 2 of 2) Frequency Range
fOUT < 2 x fXCLK AND fOUT fXCLK fOUT < fXCLK AND fOUT fXCLK / 2 fOUT < fXCLK/2 AND fOUT fXCLK / 4 fOUT < fXCLK/4 AND fOUT fXCLK / 8 fOUT < fXCLK/8 AND fOUT fXCLK / 16 fOUT < fXCLK/16 AND fOUT fXCLK / 32
ADE3700
SDIV
2 3 4 5 6 7
MD = INT(fXCLK x (2(6 + NDIV - SDIV)) / fOUT) PE = INT((215) x (MD + 1 - fXCLK x (2(6 + NDIV - SDIV)) / fOUT)) where fXCLK is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency generated by this block is fXTAL x 2(2+NDIV). For the lowest power operation, all clock sources should be set to the "zero" setting and the analog power disables should be set. In this condition, only the crystal clock domain (XCLK) is running and blocks in INCLK or DOTCLK domains may not be accessible through the IC interface. The following modules can have their clocks disabled to reduce power consumption when the chip is in steady-state mode: FLK, OSD, PGEN, DFT, and DMEAS. Also, the clock to the TCON can be disabled for non-Smart Panel applications. Note that the OSD module has a special power bypass bit that must be enabled when the OSD clock is disabled. Also, the clock to all IC registers associated with modules in the INCLK and DOTCLK domains can be disabled after the chip is configured to reduce power in steady-state mode. Note that during chip configuration, all IC clocks must be enabled. An asynchronous clock enable override signal must be disabled to allow control of individual module clock signals.
12/89
ADE3700
Global Control
Table 4: Global Registers (Sheet 1 of 4) Register Name
GLBL_NULL_ADDR GLBL_CLK_SRC_SEL_0
Addr.
0x0000 0x0001
mode
Read
Bits
[7:0] [7]
Default
Description
Chip Revision ID
0x0 0x5
Reserved DOTCLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) 0x3: INCLK source 0x4: CLKIN pin 0x5: crystal clock 0x6: 0 0x7: Reserved
R/W
[6:4]
R/W
[3:0]
0xA
INCLK source 0x0: TESTCLK pin 0x1: nc 0x2: ADC clock red 0x3: ADC clock green 0x4: ADC clock blue 0x5: SCLK freq synth 0x6: nc 0x7: LLK PLL (ADC Input) 0x8: CLKIN pin 0x9: FM freq synth 0xA: crystal clock 0xB: 0 0xC - 0xF: Reserved
GLBL_CLK_SRC_SEL_2
0x0002 R/W
[7] [6:4]
0x0 0x4
Reserved LLK CTRL CLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: LLKPLL control clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
[3] R/W [2:0] 0x4
Reserved LLK ZERO CLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: LLKPLL zero clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
13/89
Global Control
Table 4: Global Registers (Sheet 2 of 4) Register Name
GLBL_CLK_INV
ADE3700
Addr.
0x0003
mode
Bits
[7:5]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 Reserved
Description
R/W R/W R/W R/W R/W GLBL_CLK_ENABLE_0 0x0004 R/W GLBL_ANA_PWR 0x0005 R/W R/W R/W
[4] [3] [2] [1] [0] [7:1] [0] [7:5] [4] [3] [2] [1:0]
Invert LLPLL control clock Invert LLPLL zero clock Invert ADC sample clock Invert DOT clock Invert input clock Reserved Clock enable async override Reserved Blue ADC power down Green ADC power down Red ADC power down Reserved Reserved SMEAS block reset, synchronous to XCLK SRT block reset, synchronous to XCLK Frame Sync block reset, synchronous to XCLK Reserved Disable I2C auto increment SDA PMOS enable bypass I2C filter Reserved crystal oscillator enable Reserved XTAL frequency multiplier NDIV 0x0: fXCLK = 54MHz 0x1: fXCLK = 27MHz (normal) 0x2: fXCLK = 13.5MHz 0x3: Reserved
GLBL_XK_SRST
0x0006 R/W R/W R/W
[7:3] [2] [1] [0] [7:3] R/W R/W R/W [2] [1] [0] [7:1] R/W [0] [7:5] R/W [4:3]
GLBL_I2C_CTRL
0x0007
GLBL_XTAL_CTRL
0x0008
GLBL_SCLK_SYNTH_CTRL
0x0009
R/W R/W R/W
[2] [1] [0]
0x0 0x0 0x1
SCLK frequency synthesizer EXT_PLL (normal operation = 0) SCLK frequency synthesizer PLL_SEL (normal operation = 1) SCLK freq synth control disable (normal operation = 0)
14/89
ADE3700
Table 4: Global Registers (Sheet 3 of 4) Register Name
GLBL_SCLK_MD_SD
Global Control
Addr.
0x000A
mode
R/W R/W
Bits
[7:3] [2:0] [7:0] [7:0] [7:1]
Default
0x0 0x0 0x0
Description
SCLK frequency synthesizer MD, range is [16,31] SCLK frequency synthesizer SDIV, range is [0,7] SCLK frequency synthesizer PE, range is [0, 32767]
GLBL_SCLK_PE_L GLBL_SCLK_PE_H GLBL_TST_CTRL
0x000B 0x000C 0x000D
R/W R/W
0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0
Reserved functional test mode enable Reserved Compensation pad TQ (test mode) Compensation pad EN (enable) Reserved invert SCLK Reserved SCLK source select 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) 0x3: INCLK source 0x4: CLKIN pin 0x5: crystal clock 0x6: 0 0x7: Reserved
R/W GLBL_COMP_PAD_CTRL 0x000E R/W R/W GLBL_SCLK_CTRL 0x0010 R/W
[0] [7:2] [1] [0] [7:5] [4] [3]
R/W
[2:0]
GLBL_BPAD_EN
0x0011
R/W
[3:0]
0x0
For each bit n (0 to 3) in the LS nibble, 0: TCON[n] pin is TCON output 1: TCON[n] pin is input for testing
R/W GLBL_IK_SRST 0x0020 R/W R/W R/W R/W R/W R/W R/W R/W GLBL_SHADOW_EN 0x0021 R/W
[4] [7] [6] [5] [4] [3] [2] [1] [0] [7:1] [0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Port B input mode enable (production test only) Reserved DFT block reset synchronous to INCLK ADC block reset synchronous to INCLK SCALER block reset synchronous to INCLK Reserved Reserved DMEAS block reset synchronous to INCLK SMUX block reset synchronous to INCLK Reserved Shadow registers sync on frame boundary
15/89
FM Frequency Synthesizer
Table 4: Global Registers (Sheet 4 of 4) Register Name
GLBL_INCLK_GATE_CTRL
ADE3700
Addr.
0x0022
mode
Bits
[7:3]
Default
0x0 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 Reserved
Description
R/W R/W R/W GLBL_DK_SRST 0x0040 R/W R/W R/W R/W R/W R/W R/W GLBL_OSD_POWER_CTRL 0x0041 R/W GLBL_DOTCLK_GATE_CTRL 0x0042 R/W R/W R/W R/W R/W
[2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7:1] [0] [7:5] [4] [3] [2] [1] [0]
Enable DFT clock Enable DMEAS clock Enable INCLK to I2C registers Reserved PGEN block reset synchronous to DOTCLK OMUX block reset synchronous to DOTCLK APC block reset synchronous to DOTCLK OSD block reset synchronous to DOTCLK GAMMA block reset synchronous to DOTCLK OSQ block reset synchronous to DOTCLK SCALE block reset synchronous to DOTCLK Reserved OSD bypass (when clock disabled) Reserved Enable FLK clock Enable TCON clock Enable OSD clock Enable PGEN clock Enable DOTCLK to I2C registers
2.2
FM Frequency Synthesizer
The FM Frequency Synthesizer can create a clock up to eight times the crystal input clock using a digital frequency synthesizer. The modulation period and amplitude are directly controlled by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for access. The relationship of the output frequency (fOUT) to the 32-bit phase_rate value and the crystal frequency (fXCLK) is: fOUT = fXCLK * 227+NDIV / phase_rate where fOUT and fXCLK are in MHz. The maximum output frequency of the FM frequency synthesizer is fXTAL x 2(2+NDIV). Note that native duty cycle of the FM frequency synthesizer is not 50/50, so it is recommended to either enable the divide-by-two in the fm synthesizer block for frequencies up to fXCLK x 2(1+NDIV) (typically 108 MHz) or set the output mux to a double wide output mode for pixel clocks above fXCLK x 2(1+NDIV). This will ensure a 50% duty clock on the output.
16/89
ADE3700
Analog-to-Digital Converter (ADC)
Table 5: FM Frequency Synthesizer Registers Register Name
FM_FS_CTRL
Addr
0x0830
Mode
Bits
[7:4]
Default
Reserved 0x0 0x0 0x0 0x0 8000000
Description
R/W R/W R/W R/W FM_FS_PR_0 FM_FS_PR_1 FM_FS_PR_2 FM_FS_PR_3 FM_FS_AMPLITUDE FM_FS_PERIODX64 FM_FS_PULSE_EXT 0x0831 0x0832 0x0833 0x0834 0x0835 0x0836 0x0837 R/W R/W R/W R/W R/W R/W R/W
[3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] [6:3]
Clear the FM synthesizer Clear the fs accumulator Activate the frequency modulation Divide the output by 2 Phase Rate
0x0 0x80 0x0
LSB = 72 ps LSB = 1.185 us Enable Reserved
R/W
[2:0]
0x0
Value
2.3
Analog-to-Digital Converter (ADC)
The analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital filtering. The I2C interface for the ADC block is in the INCLK clock domain which must be active for programming. The relationship of input voltage, gain and offset register settings to output code is approximately as follows: output_code_8b = 457 x offset / 28 + 181 x gain x input_mV / 216 - 125 x gain x offset / 216 - 219
Table 6: ADC Registers (Sheet 1 of 2) Register
ADC_DITHER
Addr.
0x0324
Mode
Bits
[7]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
R/W R/W R/W R/W R/W
[6] [5] [4] [3] [2] [1:0]
Dither horizontally Dither vertically Dither temporally Force dither high Enable dither Reserved Offset Control, Red Channel Offset Control, Green Channel
ADC_OFFSET_R ADC_OFFSET_G
0x0326 0x0328
R/W R/W
[7:0] [7:0]
17/89
Line Lock PLL
Table 6: ADC Registers (Sheet 2 of 2) Register
ADC_OFFSET_B ADC_GAIN_R ADC_GAIN_G ADC_GAIN_B
ADE3700
Addr.
0x0329 0x032A 0x032B 0x032C
Mode
R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0
Description
Offset Control, Blue Channel Gain Control, Red Channel Gain Control, Green Channel Gain Control, Blue Channel
2.4
Line Lock PLL
The Line Lock PLL recovers a sample clock from an incoming hsync source. The response characteristics of the line lock PLL can be adjusted for optimum response time and jitter filtering. The phase of the sample clock can be digitally adjusted in steps of 289 ps (with a 27-MHz crystal). The I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for programming. The PLL filter has three ranges with independent filter parameters. When the phase detector error stays below a programmable threshold for a programmable number of input lines, the PLL filter coefficients are changed. Any phase detector error above the programmed threshold will return the filter to the appropriate level in one line. The operation is shown in Figure 3.
Figure 3: Line Lock PLL
Error <= SLOW_TOL for more than SLOW_LINE_NB of lines
Error <= LOCK_TOL for more than LOCK_LINE_NB of lines
Fast
Slow
Lock Error > LOCK_TOL
Error > SLOW_TOL
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the desired number of clocks per input line. The A and B parameters control the response of the 2nd order digital filter. A and B are composed of a linear and exponential component designated by the L and E suffix, respectively. The relationship of these numbers to the classic 2nd order damping and natural frequency are as follows: Damping = AL x 2(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE)) Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2(BE-34))
18/89
ADE3700
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 1 of 4) Register Name
LLK_PLL_CLEAR
Addr
0x0800
Mode
Bits
[7:6]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 master reset
Description
R/W R/W R/W R/W R/W R/W LLK_PLL_CTRL 0x0801 R/W R/W R/W
[5] [4] [3] [2] [1] [0] [7] [6] [5]
reset the PLL synthetic sync reset PLL offset reset PLL accumulator reset the low pass filter reset the PLL phase error Reserved
0x0 0x0
zero clock delay enable 0: normal 1: diagnostic mode -- PLL uses only fine error 0: normal 1: diagnostic -- coarse error is multiplied by 2 input hsync edge selection 0: rising edge 1: falling edge
R/W
[4]
0x0
R/W
[3]
0x0
R/W
[2]
0x0
sync on green input selection 0: composite sync (HSYNC pin) 1: sync on green (CSYNC pin)
R/W R/W LLK_PLL_MFACTOR_L LLK_PLL_MFACTOR_H LLK_PLL_HPERIOD_L LLK_PLL_HPERIOD_H LLK_PLL_PHASE_RATE_INIT_0 LLK_PLL_PHASE_RATE_INIT_1 LLK_PLL_PHASE_RATE_INIT_2 LLK_PLL_PHASE_RATE_INIT_3 LLK_PLL_PHASE_RATE_INIT_WR 0x0802 0x0803 0x0804 0x0805 0x0806 0x0807 0x0808 0x0809 0x080A R/W R/W R/W R/W R/W R/W R/W R/W R/W
[1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:1] [0]
0x0 0x0 0x0280
0: normal 1: divide PLL clock by 2 0: normal 1: free-running mode number of clocks in a line
0x0040
pulse width of synthetic hsync
0x0
initial phase rate fout = fxtal * 227+NDIV / phase_rate
Reserved When written to 1, the pll phase rate is initialized with the initial phase rate register. Self clearing.
19/89
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 2 of 4) Register Name
LLK_PLL_TC_AEF
ADE3700
Addr
0x080B
Mode
Bits
[7:4]
Default
Reserved 0xA
Description
R/W LLK_PLL_TC_BEF 0x080C R/W LLK_PLL_TC_ALF 0x080D R/W LLK_PLL_TC_BLF 0x080E R/W LLK_PLL_TC_AES 0x080F R/W LLK_PLL_TC_BES 0x0810 R/W LLK_PLL_TC_ALS 0x0811 R/W LLK_PLL_TC_BLS 0x0812 R/W LLK_PLL_TC_AEK 0x0813 R/W LLK_PLL_TC_BEK 0x0814 R/W LLK_PLL_TC_ALK 0x0815 R/W LLK_PLL_TC_BLK 0x0816 R/W LLK_PLL_TC_SLOW_TOL 0x0817 R/W
[3:0] [7:4] [3:0] [7:6] [5:0] [7:6] [5:0] [7:4] [3:0] [7:4] [3:0] [7:6] [5:0] [7:6] [5:0] [7:4] [3:0] [7:4] [3:0] [7:6] [5:0] [7:6] [5:0] [7:0]
Fast Time Constant A Exponent Reserved
0xA
Fast Time Constant B Exponent Reserved
0x20
Fast Time Constant A Linear Reserved
0x20
Fast Time Constant B Linear Reserved
0x6
Slow Time Constant A Exponent Reserved
0x6
Slow Time Constant B Exponent Reserved
0x20
Slow Time Constant A Linear Reserved
0x20
Slow Time Constant B Linear Reserved
0x6
Lock Time Constant A Exponent Reserved
0x6
Lock Time Constant B Exponent Reserved
0x20
Lock Time Constant A Linear Reserved
0x20 0x80
Lock Time Constant B Linear More than slow_line_nb lines with a phase error less than the slow_tol will set the slow status bit, and the pll will work with the slow time constant. One or more lines with a phase error more than slow_tol will reset the slow status bit, and the pll will work with the fast time constant. LSB of slow tol is approx. 200ps.
LLK_PLL_TC_SLOW_LINE_NB
0x0818
R/W
[7:0]
0x10
20/89
ADE3700
Table 7: Line Lock PLL Registers (Sheet 3 of 4) Register Name
LLK_PLL_LOCK_TOL
Line Lock PLL
Addr
0x0819
Mode
R/W
Bits
[7:0]
Default
0x20
Description
More than lock_line_nb lines with a phase error less than the lock_tol will set the lock status bit, and the pll will work with the lock time constant. One or more lines with a phase error more than lock_tol will reset the lock status bit, and the pll will work with the slow time constant. LSB of lock tol is approx. 200ps.
LLK_PLL_LOCK_LINE_NB LLK_PLL_PH_OFFSET
0x081A 0x081B
R/W R/W
[7:0] [7:0]
0x30 0x0 Phase adjustment. The maximum phase offset value is equal to phase_rate[31:21] or 0x40, whichever is higher.
LLK_PLL_PH_OFFSET_EN
0x081C
R/W
[7] [6] [5] [4:0]
0x0
phase enable skip pulse skip pulse at every rising edge of hsync Reserved
LLK_PLL_PULSE_HIGH_EXT
0x081D
R/W
[7] [6:3]
0x0
0: no pulse extend 1: extend pulse (normal) Reserved
R/W
[2:0]
0x0
pulse extend amount 0x0: minimum 0x7: maximum (normal)
LLK_PLL_STAT_LINES_L LLK_PLL_STAT_LINES_H LLK_PLL_STAT_ERROR_INC_LO W LLK_PLL_FINE_ERROR_WAIT
0x081E 0x081F 0x0820 0x0821
R/W R/W
[7:0] [7:0] [7:0] [7:4]
0x10
Number of lines to statistically analyze.
Reserved Reserved 0x0 Wait this number of CTRL_CLK cycles before updating the PLL. Reserved 0x0 0x0 0x80 0x02 PLL statistic synchronize on falling edge of vsync PLL statistic synchronize on rising edge of vsync Number of clocks in a line. Registers 0x0803 and 0x0802 are transferred to those registers according to update_on_venab_fe.
R/W LLK_PLL_STAT_ON_VSYNC 0x0822 R/W R/W LLK_PLL_MFACTOR_SHADOW_L LLK_PLL_MFACTOR_SHADOW_U 0x0823 0x0824 R/W R/W
[3:0] [7:2] [1] [0] [7:0] [7:0]
21/89
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 4 of 4) Register Name
LLK_PLL_UPDATE
ADE3700
Addr
0x0840
Mode
R
Bits
[7]
Default
Description
In free-running mode, toggles when status is updated. In one-shot mode, this bit is set when status is ready.
[6:2] R/W R/W LLK_PLL_STATUS 0x0841 R R R R LLK_PLL_PH_ERROR_L LLK_PLL_PH_ERROR_H LLK_PLL_PHASE_RATE_0 LLK_PLL_PHASE_RATE_1 LLK_PLL_PHASE_RATE_2 LLK_PLL_PHASE_RATE_3 LLK_PLL_PHASE_RATE_I_0 LLK_PLL_PHASE_RATE_I_1 LLK_PLL_PHASE_RATE_I_2 LLK_PLL_PHASE_RATE_I_3 LLK_PLL_STAT_ERROR_MEAN 0x0842 0x0843 0x0844 0x0845 0x0846 0x0847 0x0848 0x0849 0x084A 0x084B 0x084C R R R R R R R R R R R [1] [0] [7:4] [3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x0 0x0
Reserved 0: free-running mode 1: one-shot mode update enable Reserved llk overflow coarse error = 0 in slow mode in lock mode phase error LSB = approx. 200ps llk phase rate fout = fxtal * 227+NDIV / phase_rate
integral phase rate
average phase error over stat_lines phase error LSB is approx. 200ps
LLK_PLL_STAT_ERROR_PP_L LLK_PLL_STAT_ERROR_PP_H LLK_PLL_STAT_ERROR_ABS_L
0x084D 0x084E 0x084F
R R R
[7:0] [7:0] [7:0]
peak phase error over stat_lines phase error LSB is approx. 200ps sum of absolute phase errors over stat_lines phase error LSB is approx. 200ps
LLK_PLL_STAT_ERROR_ABS_H LLK_PLL_STAT_ERROR_GTX
0x0850 0x0851
R
[7:0] [7:0] Reserved
22/89
ADE3700
Sync Retiming (SRT)
2.5
Sync Retiming (SRT)
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, the SRT has the following functions:
q q q q q
Retimes all sync signals going to SMEAS into the XCLK domain. Extracts the vertical sync signal from composite sync signals (AHSYNC and ACSYNC pins) Divides clocks by 1024 for activity detection purposes. Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. Generates a coast signal in the XCLK domain for the LLPLL.
Table 8: Sync Retiming Registers (Sheet 1 of 2)
Register Name
SRTXK_CSYNC_INV
Addr
0x01E0
Mode
Bits
[7:3]
Default
0x0 0x0 0x0 0x0 0x080 Reserved
Description
R/W R/W R/W SRTXK_SOG_THR_L SRTXK_SOG_THR_H 0x01E1 0x01E2 R/W R/W
[2] [1] [0] [7:0] [7:4] [3:0]
invert filtered vert sync signal invert composite sync signal invert SOG signal SOG vert sync extractor threshold [7:0] Reserved SOG vert sync extractor threshold [11:8]
SRTXK_CSYNC_THR_L SRTXK_CSYNC_THR_H
0x01E3 0x01E4
R/W R/W
[7:0] [7:4] [3:0]
0x080
composite sync vertical sync extractor threshold [7:0] Reserved composite sync vertical sync extractor threshold [11:8] Reserved
SRTXK_VSYNC_SEL
0x01E5
R/W
[7:3] [2:0] 0x0
filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: Reserved 0x4 - 0x7: Reserved
SRTXK_VSYNC_THR_L SRTXK_VSYNC_THR_H
0x01E6 0x01E7
R/W R/W R/W
[7:0] [7:4] [3:0]
0x080
filtered vert sync delay [7:0] Reserved filtered vert sync delay [11:8]
23/89
Sync Retiming (SRT)
Table 8: Sync Retiming Registers (Sheet 2 of 2) Register Name
SRTXK_COAST_VS_SEL
ADE3700
Addr
0x01E8
Mode
Bits
[7:4]
Default
0x0 0x0 Reserved
Description
R/W
[3]
coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: Reserved 0x4: nc 0x5: nc 0x6: srt vsync (filtered vsync) 0x7: Reserved
R/W
[2:0]
0x0
SRTXK_COAST_RISE_L SRTXK_COAST_RISE_M SRTXK_COAST_RISE_H SRTXK_COAST_FALL_L SRTXK_COAST_FALL_M SRTXK_COAST_FALL_H SRTIK_HS_CTRL
0x01E9 0x01EA 0x01EB 0x01EC 0x01ED 0x01EE 0x01F0
R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
rising edge of coast, in XCLKs from vsync trigger
falling edge of coast, in XCLKs from vsync trigger
Reserved Resample clock edge to transfer hsync into the INCLK domain; depends on LLK phase offset value. 0: posedge INCLK 1: negedge INCLK
R/W
[2]
R/W
[1:0]
0x0
horz sync source select for resampling into the INCLK domain 0x0: LLPLL lock sync (normal) 0x1: ahsync pin 0x2: acsync pin 0x3: Reserved
SRTIK_VS_SEL
0x01F1 R/W
[7:2] [1:0]
0x0 0x0
Reserved vert sync source select for resampling 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: srt vsync (filtered vsync)
24/89
ADE3700
Sync Measurement
2.6
Sync Measurement
The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the results of the measurements to the system microcontroller. This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming sync signals. Input Sync Functions:
q q q
Activity Detection Sync Management Measurement
Table 9: Sync Measurement (Sheet 1 of 8)
Register Name
SMEAS_ACT_CTRL
Addr
0x0100
Mode
Bits
[7:4]
Default
0x0 0x0 0x0 Reserved
Description
R/W R/W
[3] [2]
Enable activity detection in free-running mode. Freeze results in free-running mode. No meaning in one shot mode. 0: Do not freeze the results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results. The polling bit will still toggle and the block continues to free-run; however, results will not be updated.
R/W
[1]
0x0
activity detection start. In one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete.
R/W
[0]
0x0
activity detection mode control 0: free-running 1: one shot
SMEAS_ACT_H_SMPTM_L SMEAS_ACT_H_SMPTM_H SMEAS_ACT_V_SMPTM_L SMEAS_ACT_V_SMPTM_H
0x0101 0x0102 0x0103 0x0104
R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0
Sample time value for clock or hsync activity. In units of XCLK_period*256 Sample time value for vsync activity in units of XCLK_period*256. jj Note: this number MUST be larger than hsync sample time. Minimum edge count value for clk or hsync activity. Minimum edge count value for vsync activity. timeout counter value for clk or horizontal measurement in XCLKs
SMEAS_ACT_H_MINEDGE SMEAS_ACT_V_MINEDGE SMEAS_H_TMOT_L SMEAS_H_TMOT_H
0x0105 0x0106 0x0107 0x0108
R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x4000
25/89
Sync Measurement
Table 9: Sync Measurement (Sheet 2 of 8) Register Name
SMEAS_V_TMOT_L SMEAS_V_TMOT_H SMEAS_CLEAR
ADE3700
Addr
0x0109 0x010A 0x0110
Mode
R/W R/W
Bits
[7:0] [7:0] [7:3]
Default
0x1600
Description
timeout counter value for vertical measurement in units of XCLK/256 Reserved
R/W R/W R/W SMEAS_H_CTRL 0x0111 R/W
[2] [1] [0] [7] [6]
0x0 0x0 0x0 0x0 0x0
clear sticky status bits clear all out-of-range event counters clear all result registers Reserved Enable hsync filter -- all hsync pulses less than SMEAS_FILTER_HS_WIDTH will be ignored. measure hsync in the absence of vsync enable horizontal measurement in freerunning mode horizontal event edge select 0: positive edge 1: negative edge
R/W R/W R/W
[5] [4] [3]
0x0 0x0 0x0
R/W
[2]
0x0
Freeze horizontal measurements results during free-running mode. No meaning in one shot mode. 0: Do not freeze measurement results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results. The polling bit will still toggle and the block continues to free-running; however, results will not be updated.
R/W
[1]
0x0
horizontal measurement start In one-shot mode setting this bit triggers the start of a measurement. The bit is reset to zero when the measurement is complete.
R/W
[0]
0x0
horizontal measurement mode 0: free-running 1: one shot
26/89
ADE3700
Table 9: Sync Measurement (Sheet 3 of 8) Register Name
SMEAS_V_CTRL
Sync Measurement
Addr
0x0112
Mode
Bits
[7:5]
Default
Reserved 0x0 0x0
Description
R/W R/W
[4] [3]
Enable Vertical Measurement in Freerunning mode Vertical Event Edge Select 0: positive edge 1: negative edge
R/W
[2]
0x0
Freeze vertical measurement results during free-running mode. No meaning in one shot mode. 0: Do not freeze the results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results in free-running mode. The polling bit will still toggle and the block continues to free run; however, results will not be updated.
R/W
[1]
0x0
Vertical Measurement Start In one-shot mode setting this bit triggers the start of a measurement. The bit is reset to zero when the measurement is complete.
R/W
[0]
0x0
Vertical Measurement Mode 0: free-running 1: one shot
SMEAS_H_SEL
0x0113 R/W
[7:4] [3:0] 0x0
Reserved Select a horizontal sync, enable or clock for measurement. 0x0: Analog hsync 0x1: Hsync generated from LLPLL 0x2: SOG from csync pin 0X3: NC 0X4: NC 0X5: NC 0X6: NC 0X7: NC 0X8: NC 0x9: TCON hsync 0xA: TCON data enable 0xB: INCLK div1k 0xC: DOTCLK div1k 0xD-0xF: Reserved
27/89
Sync Measurement
Table 9: Sync Measurement (Sheet 4 of 8) Register Name
SMEAS_V_SEL
ADE3700
Addr
0x0114
Mode
R/W
Bits
[7:4]
Default
0x0
Description
Selects a vertical signal for measurement of the high pulse width. 0x0: Analog vsync 0x1: Composite vsync 0x2: SOG vsync 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: TCON vsync 0x8 - 0xF: Reserved
R/W
[3:0]
0x0
Selects a vertical signal for measurement of period and polarity. 0x0: Analog vsync 0x1: Composite vsync 0x2: nc 0x3: nc 0x4: nc 0x5: nc 0x6: nc 0x7: TCON vsync
SMEAS_STATUS_MASK
0x0119
R/W
[7]
0x0
Mask bit for hsync polarity check 0: ignore 1: check
R/W
[6]
0x0
Mask bit for vsync polarity check 0: ignore 1: check
[5:4] R/W [3] 0x0
Reserved Mask bit for vert pulse width check 0: ignore 1: check
R/W
[2]
0x0
Mask bit for h per v check 0: ignore 1: check
R/W
[1]
0x0
Mask bit for h period check 0: ignore 1: check
R/W
[0]
0x0
Mask bit for v period check 0: ignore 1: check
SMEAS_H_NUM_LINES SMEAS_H_SKIP_L
0x011A 0x011B
R/W R/W
[7:0] [7:0]
0x0 0x0
Number of lines to measure for Horizontal period. Valid range is 1 to 255. Number of lines to skip before starting a horizontal measurement. The skip counter counts from the chosen vertical source and edge. [7:0]
28/89
ADE3700
Table 9: Sync Measurement (Sheet 5 of 8) Register Name
SMEAS_H_SKIP_H
Sync Measurement
Addr
0x011C
Mode
R/W
Bits
[7:4] [3:0]
Default
Reserved
Description
Number of lines to skip before starting a horizontal measurement. The skip counter counts from the chosen vertical source and edge. [11:8] 0x0 0x0 0x0 0x0 0x5 Reserved 1 = delay vsync a number of XCLKs specified in SMEAS_DELAY_VSYNC Reserved Write a rising edge to start the hv-skew measurement. Test skew limit in XCLKs. If the skew is less than this test limit, the SMEASE_SKEW_STATUS register will report an error condition. SMEAS_DELAY_VSYNC should be reprogrammed until the skew is large enough to prevent vcount ambiguity. Number of XCLKs to delay vsync. Reference value for XCLKs per horizontal event actual value = programmed value + 1
SMEAS_SKEW_CTRL
0x011D R/W
[7:3] [2] [1] R/W [0] [7:0]
SMEAS_SKEW_THRES
0x011E
R
SMEAS_DELAY_VSYNC SMEAS_REF_XK_PER_H_L SMEAS_REF_XK_PER_H_M SMEAS_REF_XK_PER_H_H SMEAS_REF_XK_PER_V_L SMEAS_REF_XK_PER_V_M SMEAS_REF_XK_PER_V_H SMEAS_REF_H_PER_V_L SMEAS_REF_H_PER_V_H SMEAS_REF_XK_V_PER_HI_L SMEAS_REF_XK_V_PER_HI_M SMEAS_REF_XK_V_PER_HI_H SMEAS_REF_POLARITY
0x011F 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2]
0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Reference value for XCLKs per vertical event actual value = programmed value + 2
Reference value for horizontal events per vertical event Reference value for vertical pulse width measurement result in XCLKs. actual value = programmed value + 1
Reserved Reference value for Hsync polarity. 0: active low 1: active high
R/W
[1]
R/W
[0]
0x0
Reference value for Vsync polarity. 0: active low 1: active high
SMEAS_XK_HTOL_EXP
0x012C
R/W
[7:4] [3:0]
0x0 0x0 0x0 0x0
Reserved Horizontal tolerance; 2n XCLKs Reserved Vertical tolerance; 2n XCLKs
SMEAS_XK_VTOL_EXP
0x012D R/W
[7:4] [3:0]
29/89
Sync Measurement
Table 9: Sync Measurement (Sheet 6 of 8) Register Name
SMEAS_HSYNC_VTOL
ADE3700
Addr
0x012E
Mode
Bits
[7:4]
Default
0x0 0x0 0x1 0x0 0x0 Reserved
Description
R/W SMEAS_FILTR_HS_WIDTH SMEAS_ACT_POLLING 0x012F 0x013F R R/W
[3:0] [7:0] [7:1] [0]
Horizontal per vertical tolerance, 2n Refer to register 0x0111 Reserved Toggle on activity status update in freerunning mode. No function in one-shot mode. Reserved Composite sync is active Vsync from SOG separator is active Comp vsync from composite sync separator is active Analog hsync is active Analog vsync is active Reserved Comp sync is stuck at 1(high)/0(low) Vsync from SOG separator is stuck at 1(high)/0(low) Comp vsync from separator is stuck at 1(high)/0(low) Analog hsync is stuck at 1(high)/0(low) Analog vsync is stuck at 1(high)/0(low) XCLKs per horizontal event - 1
SMEAS_ANA_ACT
0x0140 R R R R R
[7:5] [4] [3] [2] [1] [0] [7:5] R R R R R [4] [3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2] R R [1] [0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
SMEAS_ANA_STUCK
0x0143
SMEAS_XK_PER_H_L SMEAS_XK_PER_H_M SMEAS_XK_PER_H_H SMEAS_XK_PER_V_L SMEAS_XK_PER_V_M SMEAS_XK_PER_V_H SMEAS_H_PER_V_L SMEAS_H_PER_V_H SMEAS_SK_V_HI_L SMEAS_SK_V_HI_M SMEAS_SK_V_HI_H SMEAS_TIMEOUT_STATUS
0x0146 0x0147 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F 0x0150 0x0151
R R R R R R R R R R R
XCLKs per vertical event - 1
Horizontal events per vertical event
Vertical high time in XCLKs - 1
Reserved Indicates that the horizontal measurement timed out. Indicates that the vertical measurement timed out.
30/89
ADE3700
Table 9: Sync Measurement (Sheet 7 of 8) Register Name
SMEAS_STATUS_RANGE
Sync Measurement
Addr
0x0152
Mode
R
Bits
[7]
Default
0x0
Description
In free-running mode any of the status bits can change at the end of each measurement. In one shot mode any of the status bits can change at the completion of the measurement. The MEAS_STICKY_STATUS bit is a bitwise OR of bits[3:0] (before the bitwise OR, the mask in SMEAS_STATUS_MASK is AND in) and is sticky. The only way to reset it is for software to write a zero into this bit. This bit goes to the scaler to blank the scaler output. A write to this reg will reset it to 0. Indicates that one of the measured polarities does not match the reference value. Hsync (selected by SMEAS_H_SEL) polarity. 0: active low 1: active high
R R
[6] [5]
0x0 0x0
R
[4]
0x0
Vsync (selected by SMEAS_V_SEL) polarity. 0: active low 1: active high
R
[3]
0x0
Indicates that the vertical pulse width measurement exceeded the reference tolerance range. Indicates that the horizontal per vertical measurement exceeded the reference tolerance range. Indicates that the XCLKs per horizontal measurement exceeded the reference tolerance range. Indicates that the XCLKs per vertical measurement exceeded the reference tolerance range. Reserved Toggle on h meas free-running mode, at end of each meas. No function on one-shot mode. Toggle on v meas free-running mode, at end of each meas. No function on one-shot mode. Reserved 0: hsync to vsync skew above threshold 1: hsync to vsync skew below threshold 0: skew measurement running 1: skew measurement finished
R
[2]
0x0
R
[1]
0x0
R
[0]
0x0
SMEAS_MEAS_POLLING
0x0153 R
[7:2] [1]
0x0 0x0
R
[0]
0x0
SMEAS_SKEW_STATUS
0x0154 R R
[7:2] [1] [0]
0x0 0x0 0x0
31/89
Sync Multiplexer (SMUX)
Table 9: Sync Measurement (Sheet 8 of 8) Register Name
SMEAS_V_OUTOF_RNG
ADE3700
Addr
0x0155
Mode
R
Bits
[7:0]
Default
0x0
Description
The number of times the XCLKs per vertical reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the XCLKs per horizontal reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the horizontal per vertical reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the vertical pulse width in XCLKs reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the horizontal polarity reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the vertical polarity reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1].
SMEAS_H_OUTOF_RNG
0x0156
R
[7:0]
0x0
SMEAS_HV_OUTOF_RNG
0x0157
R
[7:0]
0x0
SMEAS_VHI_OUTOF_RNG
0x0158
R
[7:0]
0x0
SMEAS_HPOL_OUTOF_RNG
0x0159
R
[7:0]
0x0
SMEAS_VPOL_OUTOF_RNG
0x015A
R
[7:0]
0x0
2.7
Sync Multiplexer (SMUX)
The Synchronization Multiplexer (SMUX) selects a set of sync signals from the input sources and provides them to the scaler. It generates signals that are missing, depending on the capability. The MCU can select the output sync signals between the input sources and the generated signals.
Figure 4: Sync Multiplexer Block Diagram
odd data_valid hsync_internal vsync_internal enab_internal Output Signal Selector
Input Signals
Internal Signal Selector
Output Signals
Signal Generator H/V Reference Signals hcount vcount
32/89
ADE3700 2.7.1 Functional Description
Sync Multiplexer (SMUX)
The internal signal selector selects which of the input sources are to be used for the internal hsync, vsync and enab signals and is controlled by I2C register SMUX_CTRL0. The signal generator contains a horizontal and a vertical counter that are resynced using a horizontal and vertical reference signals respectively. The selection of the H/V references and the resync edge (either rising or falling) are programmed via SMUX_CTRL1[3:0]. The signal generator requires both references to be defined, or else the counters will not run properly and the generated signals (other than venab) will be invalid. The output signal selector can be programmed to output any of the internal syncs, bypassed signals such as odd and data_valid, or the generated versions of all the signals (hsync, vsync, enab, odd, valid). Vertical enable (venab) and clamp are always generated. The following table summarizes programming for typical modes.
Table 10: Sync Multiplexer Programming Table Output Source for Mode Valid Inputs Hsync
Analog Line Lock Analog Ext. Clock LLK_HSYNC LLK_VSYNC VGA_HSYNC LLK_VSYNC TESTCLK LLK
Vsync
LLK
Enab
GEN
Valid
GEN
Odd
NA
Venab
GEN
Clamp
GEN
VGA
LLK
GEN
GEN
NA
GEN
GEN
Other sources (such as composite sync) are simple variations on these basic configurations. The programmed timing values of the generated signals (such as clamp) are relative to the reference signal and edge selected. For example, if the LLK_HSYNC falling edge is selected as the horizontal reference, then all horizontal programming values are relative to it. Three signals are generated using programmable set/reset values: clamp and the two components that make up the input enable signal (horizontal and vertical enables). The henab and venab signals define the video window that the scaler operates on. The difference between the reset and set quantities is the number of pixels (h) or lines (v) in the input image. Clean wraparound is supported: the henab_set can be greater than the henab_rst. The clamp pulse should be located outside the active video area, i.e. both programmed values should be in the horizontal blanking region, typically in backporch of the incoming sync. All set/reset programming values for clamp and henab must be less than the input horizontal total. Both set/reset programming values for venab must be less than the input vertical total. The updates for the enable registers can occur in four modes: 1. No Shadowing 2. Simple Shadowing: updates occur when the upper byte of _rst is written 3. Shadowing + Blank Update: updates occur only in the next blanking region after rst_u is written 4. Shadowing + Vblank Update: updates occur in the next vblank region after rst_u is written. This mode also advances or retards the frame trigger to the scaler to prevent glitches. It takes one frame to write H and two frames to write the V-position. With large position changes, a glitch will show up. For small changes (e.g. 1) no glitch is created. The written position values are instantly available by read back, independent of shadow mode. The actual values being used by the hardware at a given time can also be read back using separate IC addresses.
33/89
Sync Multiplexer (SMUX)
ADE3700
When hsync and/or vsync is generated (e.g. when enab is the only input), the relative position of the generated pulse can be set either before or after the reference edge between -128 and +127 pixels per line.
2.7.2
Example
ADC input using line lock clock: omux_ctrl0 = 0x09 omux_ctrl1 = 0x0F omux_ctrl2 = 0x0C // select llk hsync and vsync // choose incoming hsync and vsync as references, choose rising edges // select the original hsyncs and vsyncs, along with the generated // enab and valid signals henab_set = hsync_width + hback_porch henab_rst = hsync_width + hback_porch + in_hpixel venab_set = vsync_width + vback_porch venab_rst = vsync_width + vback_porch + in_vpixel clamp_set = hsync_width + hback_porch + in_hpixel + 4 // clamp is turned on 4 after last pixel clamp_rst = hsync_width + hback_porch -4 // clamp is turned off 4 pixels before the 1st pixel
Table 11: Sync Multiplexer Registers (Sheet 1 of 4) Register Name
SMUX_CTRL0
Addr
0x0200
Mode
Bits
[7:6]
Default
0x0 0x0 Reserved
Description
R/W
[5:3]
Vsync_internal select 0x0 = 0x1 = 0x2 = 0x3 = 0x4 = Reserved llk/VGA vsync Reserved composite sync decoder Reserved
R/W
[2:0]
0x0
Hsync_internal select 0x0 = 0x1 = 0x2 = 0x3 = 0x4 = Reserved llk synthesized hsync Reserved raw VGA hsync (jitter) Reserved
34/89
ADE3700
Table 11: Sync Multiplexer Registers (Sheet 2 of 4) Register Name
SMUX_CTRL1
Sync Multiplexer (SMUX)
Addr
0x0201
Mode
R/W
Bits
[7]
Default
0x0 venab out select
Description
0: derived from enab out 1: generated internally R/W [6] 0x0 0: simple reset of hcount by href 1: self reset of hcount, used when the chosen href is intermittent, e.g. generating hsync from henab source. Vsync_out invert Hsync_out invert V_reference edge select 0: falling 1: rising R/W [2] 0x0 V_reference select 0: venab_generated 1: vsync_internal R/W [1] 0x0 H_reference edge select 0: falling 1: rising R/W [0] 0x0 H_reference select 0: enab_internal 1: hsync_internal SMUX_CTRL2 0x0202 R R/W R/W [7] [6] [5:4] 0x0 0x0 0x0 V_reference toggle output. Software odd set (for testing odd params on the bench) Odd_out select 0x0: Reserved 0x1: vsync toggle 0x2: SMUX_CTRL2[6] 0x3: Reserved Valid_out select 0: Reserved 1: valid_generated Enab_out select 0: enab_internal 1: enab_generated Vsync_out select 0: vsync_internal 1: hsync_generated Hsync_out select 0: hsync_internal 1: hsync_generated
R/W R/W R/W
[5] [4] [3]
0x0 0x0 0x0
R/W
[3]
0x0
R/W
[2]
0x0
R/W
[1]
0x0
R/W
[0]
0x0
35/89
Sync Multiplexer (SMUX)
Table 11: Sync Multiplexer Registers (Sheet 3 of 4) Register Name
SMUX_CTRL3
ADE3700
Addr
0x0203
Mode
R
Bits
[7:6]
Default
Description
venab pending state 0x0: idle 0x1: venab pending frame 1 0x2: venab pending frame 2 Wait until 0 to write venab again if in henab or venab shadow mode.
R
[5] [4]
henab pending Reserved 0x0 vtrigger reference 2'bx0: trigger ref = venab 2'b01: last pixel w/ anti-glitch 2'b11: first pixel w/ anti-glitch Anti-glitch modes work only with venab shadow mode. First/last pixel must be consistent with out_seq in this mode.
R/W
[3:2]
R/W
[1:0]
0x0
0x0: no shadow 0x1: simple shadow. When henab_rst_u is written, henab_set_l, henab_set_u, henab_rst_l take effect. When venab_rst_u is written, venab_set_l, venab_set_u, venab_rst_l take effect. 0x2: henab shadow. Wait for next available blank period to update positions after henab_rst_u or venab_rst_u is written. 0x3: venab shadow. Wait for next available vblank period to update positions after henab_rst_u or venab_rst_u is written. Venab update takes two frames. State can be watched in ctrl3[7:5]. ADC clamp signal rising edge [11:0], relative to selected H reference signal, in INCLKS (pixels) ADC clamp signal MSBs ADC clamp falling edge ADC clamp falling edge Horizontal enable start [11:0] (left edge of image) relative to the selected H reference edge in INCLKS (pixels) horizontal enable start MSBs horizontal enable end LSBs horizontal enable end MSBs vertical enable start (top edge of image) relative to the selected vertical reference edge in lines vertical enable start MSBs vertical enable end LSBs vertical enable end MSBs
SMUX_CLAMP_SET_L SMUX_CLAMP_SET_U SMUX_CLAMP_RST_L SMUX_CLAMP_RST_U SMUX_HENAB_SET_L
0x0204 0x0205 0x0206 0x0207 0x0208
R/W R/W R/W R/W R/W
[7:0] [3:0] [7:0] [3:0] [7:0]
0x0 0x0 0x0 0x0 0x0
HENAB _SET_U HENAB _RST_L HENAB _RST_U VENAB_SET_L VENAB _SET_U VENAB _RST_L VENAB _RST_U
0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F
R/W R/W R/W R/W R/W R/W R/W
[3:0] [7:0] [3:0] [7:0] [3:0] [7:0] [3:0]
0x0 0x00 0x0 0x00 0x0 0x00 0x0
36/89
ADE3700
Table 11: Sync Multiplexer Registers (Sheet 4 of 4) Register Name
HSYNC_PHASE
Data Multiplexer
Addr
0x0210
Mode
R/W
Bits
[7:0]
Default
0x00
Description
number of horizontal pixels/INCLKS that the generated hsync edge is from the reference edge. 2's complement [-128,127]
VSYNC_PHASE
0x0211
R/W
[7:0]
0x00
number of vertical lines that the generated vsync edge is from the reference edge. 2's complement [-128,127]
HENAB_SET_HW_L HENAB _SET_HW _U HENAB _RST_HW _L HENAB _RST_HW _U VENAB_SET_HW _L VENAB _SET_HW _U VENAB _RST_HW _L VENAB _RST_HW _U
0x0212 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219
R R R R R R R R
[7:0] [3:0] [7:0] [3:0] [7:0] [3:0] [7:0] [3:0]
Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing. Actual value used by hardware post shadowing.
2.8
Data Multiplexer
The Data Multiplexer provides the following functions:
q
Debug modes (e.g. bit order swap, color swap)
Table 12: Data Mux Registers
Register Name
DMUX_CHANSEL
Addr.
0x0280
Mode
Bits
[7]
Default
0x0 0x0 0x0 Reserved
Description
R/W R/W
[6] [5:3]
0: Normal 1: MSB/LSB byte flip If enabled by [2] 0x0: Reserved 0x1: R & G bytes are swapped 0x2: B & G bytes are swapped 0x3: R => G, G => B, B => R 0x4: R & B bytes are swapped 0x5: R => B, G => R, B => G 0x0, 0x6-0x7: Reserved
R/W R/W
[2] [1:0]
0x0 0x0
0: normal 1: enable color swap video source select 0x0: ADC data 0x1: nc 0x2: nc 0x3: for test only
37/89
Data Measurement (DMEAS)
ADE3700
2.9
Data Measurement (DMEAS)
The Data Measurement (DMEAS) module measures several characteristics of the data and sync signals. Data measurements are taken over a programmable window as defined by an upper left (mix_x, min_y) and a lower right (max_x, max_y), which may be the whole frame. Measurements are programmable either per color channel or over all color channels. This module computes all measurements of sync and data format that are done in the INCLK domain. The Sync Measurement module does measurements in the XCLK domain. The INCLKS per DE measurement does not use the window feature. It measures the number of INCLK per DE and returns the result for every line. All unused or reserved bits will return as zero. Windows are relative to Sync pulses. A window defined from (0,0) - (0xFFF, 0xFFF) would go from sync to sync. The reference edge to use, rising or falling, is also programmable per X and Y coordinates. SMUX should be configured to provide a positive polarity sync to the DMEAS block. All window enables are reset to 0 and will always be reset on the rising or falling edge of the sync pulse. Most algorithms can be run over separate or all color channels. Most algorithms also contain a threshold value to zero out noise and/or amplify edges. Algorithm, Color, Threshold, or Window Control changes are accepted at the end of a valid measurement so that they do not affect the current measurement in progress. Software can request measurements in one of two ways: 1. All measurements, except DE_Size, are performed in One-shot mode, which is synchronous in respect the microcontroller. 2. The DE_Size measurement can be set either to One-shot or Free-running modes. Freerunning mode is asynchronous in respect to the microcontroller. In One-shot mode, the block should indicate that the measurement is valid through an auto clear of the start condition. In Free-running mode, the block should indicate that the measurement is valid through a polling bit. In Free-running mode, a Freeze bit is provided to freeze the results. Measurements still continue with the polling bit active, however, they are not updated if the Freeze bit is set.
2.9.1
Edge Intensity
The Edge Intensity measurement is the sum of the absolute value of the delta between adjacent pixels. A programmable threshold is applied to zero out noise and amplify edges. Equation: Delta_val = abs(pixelA - pixelB) - threshold; Delta_val = Delta_val < 0? 0: Delta_val; Sum += Delta_val; For all 3 color channels: Sum += Delta_val on Red channel + Delta_val on Green channel + Delta_val on Blue channel
2.9.2
Pixel Sum
The Pixel Sum is the sum of all selected pixels for either a specific color channel or all color channels within the window specified.
2.9.3
Minimum/Maximum Pixel
This function reports the minimum and maximum pixel found within the specified window.
38/89
ADE3700 2.9.4 Pixel Cumulative Distribution (PCD)
Data Measurement (DMEAS)
The Pixel Cumulative Distribution (PCD) function reports the total number of pixels greater than (or less than) a programmable threshold. To switch between pixels greater than or pixels less than the threshold, a control bit is provided in the DMM_Mode register when requesting a measurement.
2.9.5
Horizontal Position
The Horizontal Position measures the start and end of video data in INCLKS clock cycles relative to the posedge of hsync. The Data Horizontal Start is defined as the number of INCLKS clock cycles between posedge of hsync and the "first data pixel". First data pixel is either: 1. First pixel greater than the programmable threshold value 2. First pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value The Data Horizontal End is defined as the number of INCLKS clock cycles between posedge of hsync and the "last data pixel plus one". The search for the last pixels ends at the end of a window. Last data pixel plus one is either: 1. Pixel after the last pixel that is greater than the programmable threshold value 2. Last pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value To switch between the two threshold methods used in the first and last pixel, a control bit is provided in the DMM_Mode register when requesting a measurement. The first and last pixels are measured for each line, and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. The intention is for "last data pixel plus one" minus "first data pixel" is to equal the horizontal width of the video format.
2.9.6
Vertical Position
The Vertical Position measures the start and end of video data in hsyncs relative to the posedge of vsync. The Data Vertical Start is defined as the number of hsyncs signals between the positive edge of the vsync signal and the "first data pixel line". First data pixel line definition is the first line with at least one pixel that is greater then the programmable threshold. The Data Vertical End is defined as the number of hsyncs between posedge of vsync and the "first blanking line after data plus one". The first blanking line is detected then confirmed that each subsequent line contains no data pixels. The confirmation of the first blanking line measurement ends at the posedge of vsync. The first blanking line after data definition is the row after the last row with at least one pixel greater than the programmable threshold. The first and last data pixel lines are measured within a frame and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. The intention is for "data vertical end plus one" minus "data vertical start" is to equal the vertical height of the video format.
39/89
Data Measurement (DMEAS) 2.9.7 DE Size
ADE3700
The DE Size measures the number of INCLKS clock cycles per data enable. It is useful for DVI inputs to exactly measure the input image horizontal size. At the end of the measurement (DE falling edge), the measured value is compared to a programmed expected value a programmed threshold. If the expected value is within the threshold, the DE_size_mismatch flag is not set. If the measured size is outside of the threshold, the DE_size_mismatch flag is set. In Free-running mode, the results are updated every line. The DE_size_mismatch flag is set at DE falling edge and reset at DE rising edge. In One-shot mode, the results are updated once and stay that way until they are cleared by software. The DE_size_mismatch flag can only be cleared when the reset flag bit is set by software.
Table 13: DMEAS Output Register Mapping ALG_SEL = 00
DMEAS_DATA_0 DMEAS_DATA_1 DMEAS_DATA_2 DMEAS_DATA_3 DMEAS_DATA_4 DMEAS_DATA_5 DMEAS_DATA_6 DMEAS_DATA_7 EDGE_OUT [7:0] EDGE_OUT [15:8] EDGE_OUT [23:16] EDGE_OUT [31:24] PSUM_OUT [7:0] PSUM_OUT [15:8] PSUM_OUT [23:16] PSUM_OUT [31:24]
ALG_SEL = 01
MIN_OUT [7:0] MAX_OUT [7:0] PCD_OUT [7:0] PCD_OUT [15:8] PCD_OUT [23:16] 8'h00 8'h00 8'h00
ALG_SEL = 10
HPOS_MIN [7:0] HPOS_MIN [11:8] HPOS_MAX [7:0] HPOS_MAX [11:8] VPOS_MIN [7:0] VPOS_MIN [11:8] VPOS_MAX [7:0] VPOS_MAX [11:8]
ALG_SEL = 11
DE_SIZE_OUT [7:0] DE_SIZE_OUT [15:8] DE_MISMATCH_FLAG 8'h00 8'h00 8'h00 8'h00 8'h00
Table 14: Data Measurement Registers (Sheet 1 of 3) Register Name
DMEAS_AEC_CTRL
Addr
0x0900
Mode
Bits
[7:6]
Default
0x0 color select 00: all 01: red 10: green 11: blue
Description
R/W
[5]
0x0
vsync edge select 0: rising edge 1: falling edge hsync edge select 0: rising edge 1: falling edge interlace mode enable 0: use data valid (tv mode only) 1: use data enable for data valid algorithm select 00 = Edge Intensity & Pixel Sum 01 = Min / Max & PCD 10 = H position and V position 11 = DE size
R/W
[4]
0x0
R/W R/W R/W
[3] [2] [1:0]
0x0 0x0 0x0
40/89
ADE3700
Data Measurement (DMEAS)
Table 14: Data Measurement Registers (Sheet 2 of 3)
Register Name
DMEAS_MODE_CTRL
Addr
0x0901
Mode
R/W R/W R/W R/W R/W R/W R/W
Bits
[7] [6] [5] [4] [3] [1] [0] [7:0] [7:0] [7:4]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Reset the DE mismatch flag DE_freeze enable DE_one shot mode enable 0: Listen to odd frame only 1: Listen to even frame only Threshold Mode Bit Polling Bit Data Measurement Start Threshold value for selected algorithm Min. X window [7:0] (bits[3:0] read back `0'. Reserved Min. X window [11:8] (relative to hsync)
DMEAS_THRESHOLD DMEAS_WIN_MIN_X_L DMEAS_WIN_MIN_X_H
0x0902 0x0903 0x0904
R/W R/W
R/W DMEAS_WIN_MAX_X_L DMEAS_WIN_MAX_X_H 0x0905 0x0906 R/W R/W
[3:0] [7:0] [7:4] [3:0] 0xFFF
Max. X window [7:0] (bits[3:0] read back `0'. Reserved Max. X window [11:8] Relative to hsync, must be less than input horizontal total (LLK_LINELEN for analog input).
DMEAS_WIN_MIN_Y_L DMEAS_WIN_MIN_Y_H
0x0907 0x0908
R/W
[7:0] [7:4]
0x0
Min. Y window [7:0] (bits[3:0] read back `0'. Reserved Min. Y window [11:8] (relative to vsync)
R/W DMEAS_WIN_MAX_Y_L DMEAS_WIN_MAX_Y_H 0x0909 0x090A R/W DMEAS_DE_REF_L DMEAS_DE_REF_L DMEAS_DE_TOL DMEAS_DATA_0 DMEAS_DATA_1 DMEAS_DATA_2 DMEAS_DATA_3 DMEAS_DATA_4 DMEAS_DATA_5 DMEAS_DATA_6 DMEAS_DATA_7 0x090B 0x090C 0x090D 0x090E 0x090F 0x0910 0x0911 0x0912 0x0913 0x0914 0x0915 R/W R/W R/W R R R R R R R R R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xFFF
Max. Y window [7:0] (bits[3:0] read back `0'. Reserved Max. Y window [11:8] (relative to vsync) DE_size expected result [7:0] DE_size expected result [15:8] DE_tolerance value For details, refer to Table 13.
41/89
LCD Scaler
Table 14: Data Measurement Registers (Sheet 3 of 3) Register Name
DMEAS_SCR_PAD_0 DMEAS_SCR_PAD_1 DMEAS_SCR_PAD_2 DMEAS_SCR_PAD_3 DMEAS_SCR_PAD_4 DMEAS_SCR_PAD_5 DMEAS_SCR_PAD_6 DMEAS_SCR_PAD_7 DMEAS_SCR_PAD_8 DMEAS_SCR_PAD_9 DMEAS_SCR_PAD_10 DMEAS_SCR_PAD_11 DMEAS_SCR_PAD_12 DMEAS_SCR_PAD_13 DMEAS_SCR_PAD_14 DMEAS_SCR_PAD_15
ADE3700
Addr
0x0934 0x0916 0x0917 0x0918 0x0919 0x091A 0x091B 0x091C 0x091E 0x091F 0x0920 0x0921 0x0922 0x0923 0x0924 0x0925
Mode
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0
Description
Scratch Pad Registers
2.10
LCD Scaler
The LCD Scaler module resizes images from one resolution to another. It employs a 3x3 nonseparable scaling filter which performs a dot product of the input pixel values with a weighting vector that is computed from the chosen filtering function. To sharpen text without introducing excessive artifacts, the output pixel's contrast level is adjusted based on the context value measured over a 3x3 grid in the relevant area of the source image. For proper scaler operation, the SCLK frequency must be set greater than the max of DCLK and IN_HPIXEL x DCLK_FREQ / (DEST_HPIXEL x PIXEL_AVG).
Table 15: LCD Scaler Registers (Sheet 1 of 3) Register Name Addr
0x0A01 0x0A02 0x0A03 0x0A04 0x0A05 0x0A06 0x0A07 0x0A08 0x0A09
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [0] [7:0] [7:0]
Default
0x0
Description
Input Horizontal Resolution Bits [3:0] must be set to zero.
SCL_SRC_HPIX_L SCL_SRC_HPIX_H SCL_SRC_VPIX_L SCL_SRC_VPIX_H SCL_SCALEFACH_L SCL_SCALEFACH_M SCL_SCALEFACH_H SCL_SCALEFACV_L SCL_SCALEFACV_H
0x0
Input Vertical Resolution Bits[3:0] must be set to 0.
0x0 0x0 0x0 0x0 0x0
17-bit Horizontal Scale Factor = (in_hpixel << 16) / dest_hpixel + 0.5
16-bit Vertical Scale Factor = (in_vpixel << 15) / dest_vpixel + 0.5
42/89
ADE3700
Table 15: LCD Scaler Registers (Sheet 2 of 3) Register Name
SCL_ORIGHPOS_0 SCL_ORIGHPOS_1 SCL_ORIGHPOS_2 SCL_ORIGHPOS_3 SCL_ORIGVPOS_E_0 SCL_ORIGVPOS_E_1 SCL_ORIGVPOS_E_2 SCL_ORIGVPOS_E_3 SCL_THRES_SLOPE
LCD Scaler
Addr
0x0A0A 0x0A0B 0x0A0C 0x0A0D 0x0A0E 0x0A0F 0x0A10 0x0A11 0x0A16
Mode
R/W R/W R/W RW R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [2:0] [7:6]
Default
0x0 0x0 0x0 0x0 0x0
Description
2's complement, signed number 27-bit horizontal position of the first output pixel =(-dest_hpos * scalefactor_h) >> 5
0x0
2's complement, signed number 27-bit vertical position of the first output pixel of the even frame = (-dest_vpos_e * scalefactor_v) >> 5
0x0 0x28 0x40 0x0 0x2 0x0 0x0 0x0
Reserved Slope of the contrast amplification function Offset of the contrast amplification function [7:0] Reserved Offset of the contrast amplification function [9:8] Reserved 0: Normal 1: TCON control of contrast amplification 0: Contrast Amplification enabled 1: Bypass Contrast Amplification Reserved
R/W SCL_THRES_OFFSET_L SCL_THRES_OFFSET_H 0x0A17 0x0A18 R/W SCL_CBBYPASS 0x0A19 R/W R/W
[5:0] [7:0] [7:2] [1:0] [7:2] [1]
R/W SCL_CON_CAL_SEL 0x0A1A R/W SCL_TESTCON 0x0A1B R/W
[0] [7:1] [0] [7:2] [1:0]
0x0
0: Context = max of RGB pk-pk 1: Context = sum of RGB pk-pk 6-bit contrast amplification test data
0x0
0x0, 0x3: normal 0x1: force input data into the contrast amplification function to bits [7:2] 0x2: force the output context data to be bits [5:2]
SCL_LUT1 SCL_LUT2 SCL_LUT3 SCL_LUT4 SCL_LUT5 SCL_LUT6
0x0A1C 0x0A1D 0x0A1E 0x0A1F 0x0A20 0x0A21
R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0xFA 0xF7 0xF7 0xFC 0x2 0x0D
Sigmoidal Function LUT Entry 1, 8-bit 2's complement Sigmoidal Function LUT Entry 2, 8-bit 2's complement Sigmoidal Function LUT Entry 3, 8-bit 2's complement Sigmoidal Function LUT Entry 4, 8-bit 2's complement Sigmoidal Function LUT Entry 5, 8-bit 2's complement Sigmoidal Function LUT Entry 6, 8-bit 2's complement
43/89
LCD Scaler
Table 15: LCD Scaler Registers (Sheet 3 of 3) Register Name
SCL_LUT7 SCL_LUT8 SCL_LUT9 SCL_LUT10 SCL_LUT11 SCL_LUT12 SCL_LUT13 SCL_LUT14 SCL_LUT15 SCL_BGCOLOR_R SCL_BGCOLOR_G SCL_BGCOLOR_B SCL_BCOLOR_CTRL
ADE3700
Addr
0x0A22 0x0A23 0x0A24 0x0A25 0x0A26 0x0A27 0x0A28 0x0A29 0x0A2A 0x0A2B 0x0A2C 0x0A2D 0x0A2E
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] [6]
Default
0x17 0x21 0x28 0x2C 0x2C 0x28 0x21 0x17 0x0C 0x0 0x0 0x0 0x0 0x0
Description
Sigmoidal Function LUT Entry 7, 8-bit 2's complement Sigmoidal Function LUT Entry 8, 8-bit 2's complement Sigmoidal Function LUT Entry 9, 8-bit 2's complement Sigmoidal Function LUT Entry 10, 8-bit 2's complement Sigmoidal Function LUT Entry 11, 8-bit 2's complement Sigmoidal Function LUT Entry 12, 8-bit 2's complement Sigmoidal Function LUT Entry 13, 8-bit 2's complement Sigmoidal Function LUT Entry 14, 8-bit 2's complement Sigmoidal Function LUT Entry 15, 8-bit 2's complement Red Component of background color Green Component of background color Blue Component of background color 0: Normal 1: Force image to background color Top & Bottom Border Control 0: pixel replicating 1: background color blending
R/W
[5]
0x0
Left & Right Border Control: 0: pixel replicating 1: background color blending
R/W
[4]
0x0
Force output data as described in bit [1] when the maximum output vertical is reached. Force output data as described in bit [1] when an abnormal condition is detected by the sync measurement module. When the scaler is not running, force the output data to black if this bit is 0 or to the background color if the bit is 1. If an abnormality is detected in the sync measurement module or if the maximum output vertical total has been reached, force the output data to black if this bit is 0 or to white if this bit is 1. During blanking, force output data to black if this bit is 0 or to the background color if this bit is 1.
R/W
[3]
0x0
R/W
[2]
0x0
R/W
[1]
0x0
R/W
[0]
0x0
44/89
ADE3700
Output Sequencer
2.11
Output Sequencer
The Output Sequencer module synchronizes timing for the output video interface. It allows sufficient flexibility to support a broad range of Smart Panel applications as well using the Output Timing Controller (TCON) module, refer to Section 2.12 for more details. The timing unit is based on horizontal and vertical counters, which are locked with the input video stream.
Figure 5: Output Sequencer and Timing Controller Block Diagram
I2C Interface
timing unit horizontal vertical
delay
vert_start
signal generation fixed (OSQ) programmable (TCON)
hs, vs, den
tcon [o:13]
2.11.1 Frame Synchronization
Due to the limited pixel memory of the chip, the output active video needs to be perfectly synchronized with the input active video. This mode of operation is called Frame Lock.
Figure 6: Frame Lock Operation
2.11.2 Timing Unit
The Timing Unit consists of a 12-bit horizontal and 12-bit vertical counter. It is synchronized with the input video stream.
2.11.3 Signal Generation
The Signal Generation unit can generate all fixed control signals like hsync, vsync and data enable as well as those required to run the internal data path. The fixed control signals appear on the
45/89
Output Sequencer
ADE3700
alternate output sync pins (AHS, AUS, ADE) for applications that do not require the more sophisticated timing control provided by the programmable TCON module.
Table 16: Output Sequencer Registers (Sheet 1 of 2) Register Name
OSQ_CONTROL
Addr
0x0BC1
Mode
R R/W R/W R/W
Bits
[7] [6] [5] [4]
Default
Description
OUT_VMAX detected, sticky bit
0x0 0x0 0x0
OUT_VMAX detect reset Interlace Enable Fractional Line Extend 0: +1 1: +2
R/W
[3]
0x0
Frame Lock Reference 0: Last Input Pixel 1: First Input Pixel
R/W
[2]
0x0
Frame Lock Selection 0: Last Line Variable 1: Fixed Line Length
R R/W
[1] [0] 0x0
Shutdown ready - current frame has completed, panel can now be shut down Run sequencer when 1, otherwise stop at the end of the frame and set shutdown ready flag (bit [1]) The fraction of lines (/256) that are extended Nominal Output Horizontal Total [7:0] Reserved 0x0 0x0 Nominal Output Horizontal Total [11:8] minimum output vertical total, used to rearm for vert_enab trigger [7:0] Reserved 0x0 0x0 Minimum Output Vertical Total, used to rearm for vert_enab triggers [11:8] Maximum Output Vertical Total, prevents panel burn with loss of vert_enab trigger [7:0] Reserved 0x0 0x0 Maximum Output Vertical Total, prevents panel burn with loss of vert_enab triggers [11:8] Delay of the VERT_ENAB signal to the reset of the horizontal and vertical counters, even and non-interlaced modes [15:0]
OSQ_CLOCK_FRAC OSQ_OUT_HTOTAL_L OSQ_OUT_HTOTAL_H
0x0BC2 0x0BC3 0x0BC4
R/W R/W
[7:0] [7:0] [7:4]
0x0 0x0
R/W OSQ_OUT_VTOTAL_MIN_L OSQ_OUT_VTOTAL_MIN_H 0x0BC5 0x0BC6 R/W OSQ_VTOTAL_MAX_L OSQ_VTOTAL_MAX_H 0x0BC7 0x0BC8 R/W OSQ_VERTEN_DLY_E_L 0x0BC9 R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0]
OSQ_VERTEN_DLY_E_M OSQ_VERTEN_DLY_E_H
0x0BCA 0x0BCB
R/W
[7:0] [7:4]
0x0 Reserved 0x0 Delay of the VERT_ENAB signal to the reset of the horizontal and vertical counters, even and non-interlaced [19:16]
R/W
[3:0]
46/89
ADE3700
Table 16: Output Sequencer Registers (Sheet 2 of 2) Register Name
OSQ_VERTEN_DLY_O_L
Output Sequencer
Addr
0x0BCC
Mode
R/W
Bits
[7:0]
Default
0x0
Description
Delay of the VERT_ENAB signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [15:0]
OSQ_VERTEN_DLY_O_M OSQ_VERTEN_DLY_O_H
0x0BCD 0x0BCE
R/W
[7:0] [7:4]
0x0 0x0 0x0 Reserved Delay of the VERT_ENAB signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [19:16] Vertical count at which VSYNC goes high [7:0] Reserved vertical count at which VSYNC goes high [11:8] Vertical count at which VSYNC goes low [7:0] Reserved Vertical count at which VSYNC goes low [11:8] Horizontal count at which HSYNC goes high [7:0] Reserved Horizontal count at which HSYNC goes high [11:8] 0x0 0x0 0x0 0x0 0x0 0x0 Horizontal count at which HSYNC goes low [7:0] Reserved Horizontal count at which HSYNC goes low [11:8] Horizontal count at which ENAB goes high [7:0] Reserved Horizontal count at which ENAB goes high [11:8] value must be greater than 0x01C
R/W
[3:0]
OSQ_VSYNC_SET_L OSQ_VSYNC_SET_H
0x0BCF 0x0BD0
R/W
[7:0] [7:4]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
R/W OSQ_VSYNC_RST_L OSQ_VSYNC_RST_H 0x0BD1 0x0BD2 R/W OSQ_HSYNC_SET_L OSQ_HSYNC_SET_H 0x0BD3 0x0BD4 R/W OSQ_HSYNC_RST_L OSQ_HSYNC_RST_H 0x0BD5 0x0BD6 R/W OSQ_HENAB_SET_L OSQ_HENAB_SET_H 0x0BD7 0x0BD8 R/W R/W R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0]
OSQ_HENAB_RST_L OSQ_HENAB_RST_H
0x0BD9 0x0BDA
R/W
[7:0] [7:4]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Horizontal count at which ENAB goes low [7:0] Reserved Horizontal count at which ENAB goes low [11:8] Vertical count at which ENAB goes high [7:0] Reserved Vertical count at which ENAB goes high [11:8] Vertical count at which ENAB goes low [7:0] Reserved Vertical count at which ENAB goes low [11:8] Vertical Counter /16 indicating the current frame position
R/W OSQ_VENAB_SET_L OSQ_VENAB_SET_H 0x0BDB 0x0BDC R/W OSQ_VENAB_RST_L OSQ_VENAB_RST_H 0x0BDD 0x0BDE R/W OSQ_OUT_VCOUNT 0x0BDF R R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0]
47/89
Timing Controller (TCON)
ADE3700
2.12
Timing Controller (TCON)
The Output Timing Controller module provides timing for Smart Panel applications and other applications that are sensitive to output synchronization timing. The timing unit is based on horizontal and vertical counters, which are locked with the output video stream. A set of programmable comparators provides all necessary time events to generate the signals for the driver interface. Please refer to the Programming Tool User's Manual and to the "Using TCON Outputs" application note for more details.
Table 17: TCON Registers (Sheet 1 of 7) Register Name Addr.
0x0B00 R/W R/W R/W
Mode
Bits
[7:3] [2] [1] [0] [7:0] [7:5] [4] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
Reserved 0x0 0x0 0x0 0x0
Description
TCON_CONTROL
0: no TCON pipe delay matching 1: TCON pipe delay enabled (normal) Initialize SRTDs Enable TCON count comparison value [7:0] Reserved 0: horizontal count compare 1: vertical count compare count comparison value [11:8]
TCON_COMP_0_L TCON_COMP_0_H
0x0B10 0x0B11
R/W R/W R/W R/W
TCON_COMP_1_L TCON_COMP_1_H TCON_COMP_2_L TCON_COMP_2_H TCON_COMP_3_L TCON_COMP_3_H TCON_COMP_4_L TCON_COMP_4_H TCON_COMP_5_L TCON_COMP_5_H TCON_COMP_6_L TCON_COMP_6_H TCON_COMP_7_L TCON_COMP_7_H TCON_COMP_8_L TCON_COMP_8_H TCON_COMP_9_L TCON_COMP_9_H
0x0B12 0x0B13 0x0B14 0x0B15 0x0B16 0x0B17 0x0B18 0x0B19 0x0B1A 0x0B1B 0x0B1C 0x0B1D 0x0B1E 0x0B1F 0x0B20 0x0B21 0x0B22 0x0B23
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
48/89
ADE3700
Table 17: TCON Registers (Sheet 2 of 7) Register Name
TCON_COMP_10_L TCON_COMP_10_H TCON_COMP_11_L TCON_COMP_11_H TCON_COMP_12_L TCON_COMP_12_H TCON_COMP_13_L TCON_COMP_13_H TCON_COMP_14_L TCON_COMP_14_H TCON_COMP_15_L TCON_COMP_15_H TCON_COMP_16_L TCON_COMP_16_H TCON_COMP_17_L TCON_COMP_17_H TCON_COMP_18_L TCON_COMP_18_H TCON_COMP_19_L TCON_COMP_19_H TCON_COMP_20_L TCON_COMP_20_H TCON_COMP_21_L TCON_COMP_21_H TCON_COMP_22_L TCON_COMP_22_H TCON_COMP_23_L TCON_COMP_23_H TCON_COMP_24_L TCON_COMP_24_H TCON_COMP_25_L TCON_COMP_25_H TCON_COMP_26_L TCON_COMP_26_H
Timing Controller (TCON)
Addr.
0x0B24 0x0B25 0x0B26 0x0B27 0x0B28 0x0B29 0x0B2A 0x0B2B 0x0B2C 0x0B2D 0x0B2E 0x0B2F 0x0B30 0x0B31 0x0B32 0x0B33 0x0B34 0x0B35 0x0B36 0x0B37 0x0B38 0x0B39 0x0B3A 0x0B3B 0x0B3C 0x0B3D 0x0B3E 0x0B3F 0x0B40 0x0B41 0x0B42 0x0B43 0x0B44 0x0B45
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
Refer to TCON_COMP_0 for definition
v to TCON_COMP_0 for definition
49/89
Timing Controller (TCON)
Table 17: TCON Registers (Sheet 3 of 7) Register Name
TCON_COMP_27_L TCON_COMP_27_H TCON_SRTD_0
ADE3700
Addr.
0x0B46 0x0B47 0x0B50
Mode
R/W R/W
Bits
[7:0] [7:0] [7:4]
Default
0x0 0x0 0x0 0x0 0x0 Reserved
Description
Refer to TCON_COMP_0 for definition
R/W R/W
[3] [2:0]
SRTD initialization state 0x0: f (A&B,&C&D,0,0) 0x1: f (A&B,&C&D,0,0) 0x2: f (A&B,&C&D,0,0) 0x3: f (0,0,A&B,0) 0x4: f (0,0,0,A&B) 0x5: f (0,0,0,A|B) 0x6: f (0,0,0,A^B) 0x7: f (0,0,0,!(A&B)) where f(Set, Reset, Toggle, Dflop) is a programmable logic/flop element
TCON_SRTD_1 TCON_SRTD_2 TCON_SRTD_3 TCON_SRTD_4 TCON_SRTD_5 TCON_SRTD_6 TCON_SRTD_7 TCON_SRTD_8 TCON_SRTD_9 TCON_SRTD_10 TCON_SRTD_11 TCON_SRTD_12 TCON_SRTD_13 TCON_SRTD_14 TCON_SRTD_15 TCON_SRTD_16 TCON_SRTD_17 TCON_SRTD_18 TCON_SRTD_19 TCON_SRTD_20 TCON_SRTD_21 TCON_SRTD_22 TCON_SRTD_23 TCON_SRTD_24 TCON_SRTD_25
0x0B51 0x0B52 0x0B53 0x0B54 0x0B55 0x0B56 0x0B57 0x0B58 0x0B59 0x0B5A 0x0B5B 0x0B5C 0x0B5D 0x0B5E 0x0B5F 0x0B60 0x0B61 0x0B62 0x0B63 0x0B64 0x0B65 0x0B66 0x0B67 0x0B68 0x0B69
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition.
50/89
ADE3700
Table 17: TCON Registers (Sheet 4 of 7) Register Name
TCON_SRTD_26 TCON_SRTD_27 TCON_SRTD_28 TCON_SRTD_29 TCON_SRTD_30 TCON_SRTD_31 TCON_X_0
Timing Controller (TCON)
Addr.
0x0B6A 0x0B6B 0x0B6C 0x0B6D 0x0B6E 0x0B6F 0x0B80
Mode
R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:6]
Default
0x0 0x0 0x0 0x0 0x0 0x0
Description
Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Refer to TCON_SRTD_0 for definition. Reserved
R/W TCON_X_1 TCON_X_2 TCON_X_3 TCON_X_4 TCON_X_5 TCON_X_6 TCON_X_7 TCON_X_8 TCON_X_9 TCON_X_10 TCON_X_11 TCON_X_12 TCON_X_13 TCON_X_14 TCON_X_15 TCON_X_16 TCON_X_17 0x0B81 0x0B82 0x0B83 0x0B84 0x0B85 0x0B86 0x0B87 0x0B88 0x0B89 0x0B8A 0x0B8B 0x0B8C 0x0B8D 0x0B8E 0x0B8F 0x0B90 0x0B91 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[5:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
input selection for SRTD_0.A input selection for SRTD_0.B (Refer to Table 18 for definition) input selection for SRTD_1.A (Refer to Table 18 for definition) input selection for SRTD_1.B (Refer to Table 18 for definition) input selection for SRTD_2.A (Refer to Table 18 for definition) input selection for SRTD_2.B (Refer to Table 18 for definition) input selection for SRTD_3.A (Refer to Table 18 for definition) input selection for SRTD_3.B (Refer to Table 18 for definition) input selection for SRTD_4.A (Refer to Table 18 for definition) input selection for SRTD_4.B (Refer to Table 18 for definition) input selection for SRTD_5.A (Refer to Table 18 for definition) input selection for SRTD_5.B (Refer to Table 18 for definition) input selection for SRTD_6.A (Refer to Table 18 for definition) input selection for SRTD_6.B (Refer to Table 18 for definition) input selection for SRTD_7.A (Refer to Table 18 for definition) input selection for SRTD_7.B (Refer to Table 18 for definition) input selection for SRTD_8.A (Refer to Table 18 for definition) input selection for SRTD_8.B (Refer to Table 18 for definition)
51/89
Timing Controller (TCON)
Table 17: TCON Registers (Sheet 5 of 7) Register Name
TCON_X_18 TCON_X_19 TCON_X_20 TCON_X_21 TCON_X_22 TCON_X_23 TCON_X_24 TCON_X_25 TCON_X_26 TCON_X_27 TCON_X_28 TCON_X_29 TCON_X_30 TCON_X_31 TCON_X_32 TCON_X_33 TCON_X_34 TCON_X_35 TCON_X_36 TCON_X_37 TCON_X_38 TCON_X_39
ADE3700
Addr.
0x0B92 0x0B93 0x0B94 0x0B95 0x0B96 0x0B97 0x0B98 0x0B99 0x0B9A 0x0B9B 0x0B9C 0x0B9D 0x0B9E 0x0B9F 0x0BA0 0x0BA1 0x0BA2 0x0BA3 0x0BA4 0x0BA5 0x0BA6 0x0BA7
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
input selection for SRTD_9.A (Refer to Table 18 for definition) input selection for SRTD_9.B (Refer to Table 18 for definition) input selection for SRTD_10.A (Refer to Table 18 for definition) input selection for SRTD_10.B (Refer to Table 18 for definition) input selection for SRTD_11.A (Refer to Table 18 for definition) input selection for SRTD_11.B (Refer to Table 18 for definition) input selection for SRTD_12.A (Refer to Table 18 for definition) input selection for SRTD_12. (Refer to Table 18 for definition) input selection for SRTD_13.A (Refer to Table 18 for definition) input selection for SRTD_13.B (Refer to Table 18 for definition) input selection for SRTD_14.A (Refer to Table 18 for definition) input selection for SRTD_14.B (Refer to Table 18 for definition) input selection for SRTD_15.A (Refer to Table 18 for definition) input selection for SRTD_15.B (Refer to Table 18 for definition) input selection for SRTD_16.A (Refer to Table 18 for definition) input selection for SRTD_16.B (Refer to Table 18 for definition) input selection for SRTD_17.A (Refer to Table 18 for definition) input selection for SRTD_17.B (Refer to Table 18 for definition) input selection for SRTD_18.A (Refer to Table 18 for definition) input selection for SRTD_18.B (Refer to Table 18 for definition) input selection for SRTD_19.A (Refer to Table 18 for definition) input selection for SRTD_19.B (Refer to Table 18 for definition)
52/89
ADE3700
Table 17: TCON Registers (Sheet 6 of 7) Register Name
TCON_X_40 TCON_X_41 TCON_X_42 TCON_X_43 TCON_X_44 TCON_X_45 TCON_X_46 TCON_X_47 TCON_X_48 TCON_X_49 TCON_X_50 TCON_X_51 TCON_X_52 TCON_X_53 TCON_X_54 TCON_X_55 TCON_X_56 TCON_X_57 TCON_X_58 TCON_X_59 TCON_X_60 TCON_X_61
Timing Controller (TCON)
Addr.
0x0BA8 0x0BA9 0x0BAA 0x0BAB 0x0BAC 0x0BAD 0x0BAE 0x0BAF 0x0BB0 0x0BB1 0x0BB2 0x0BB3 0x0BB4 0x0BB5 0x0BB6 0x0BB7 0x0BB8 0x0BB9 0x0BBA 0x0BBB 0x0BBC 0x0BBD
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
input selection for SRTD_20.A (Refer to Table 18 for definition) input selection for SRTD_20.B (Refer to Table 18 for definition) input selection for SRTD_21.A (Refer to Table 18 for definition) input selection for SRTD_21.B (Refer to Table 18 for definition) input selection for SRTD_22.A (Refer to Table 18 for definition) input selection for SRTD_22.B (Refer to Table 18 for definition) input selection for SRTD_23.A (Refer to Table 18 for definition) input selection for SRTD_23.B (Refer to Table 18 for definition) input selection for SRTD_24.A (Refer to Table 18 for definition) input selection for SRTD_24.B (Refer to Table 18 for definition) input selection for SRTD_25.A (Refer to Table 18 for definition) input selection for SRTD_25.B (Refer to Table 18 for definition) input selection for SRTD_26.A (Refer to Table 18 for definition) input selection for SRTD_26.B (Refer to Table 18 for definition) input selection for SRTD_27.A (Refer to Table 18 for definition) input selection for SRTD_27.B (Refer to Table 18 for definition) input selection for SRTD_28.A (Refer to Table 18 for definition) input selection for SRTD_28.B (Refer to Table 18 for definition) input selection for SRTD_29.A (Refer to Table 18 for definition) input selection for SRTD_29.B (Refer to Table 18 for definition) input selection for SRTD_30.A (Refer to Table 18 for definition) input selection for SRTD_30.B (Refer to Table 18 for definition)
53/89
Pattern Generator
Table 17: TCON Registers (Sheet 7 of 7) Register Name
TCON_X_62 TCON_X_63
ADE3700
Addr.
0x0BBE 0x0BBF
Mode
R/W R/W
Bits
[7:0] [7:0]
Default
0x0 0x0
Description
input selection for SRTD_31.A (Refer to Table 18 for definition) input selection for SRTD_31.B (Refer to Table 18 for definition)
Table 18: Input Selection Values Value
0x00 0x01 0x02 0x03 0x04 - 0x1F 0x20 - 0x37 0x38 0 1 External TCON input pin I2C SRTD init bit comp0 - comp27 SRTD8 - SRTD31 2 frame + 1 line + 2 pixel toggle
Description
Value
0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
Description
2 frame + 2 line + 1 pixel toggle HCOUNT[0] HCOUNT[1] VCOUNT[0] VCOUNT[1] FCOUNT[0] FCOUNT[1]
2.13
Pattern Generator
The integrated Pattern Generator gives the ability to display a set of graphic patterns to help debugging systems and test LCD panels. It is located ahead of the color management block, so all generated colors are subject to further transforms. The screen can be split into a programmable grid of up to 8x8 areas. In each of these areas, it is possible to display one of two independent programmable patterns.
2.13.1 Screen Split
A set of eight Grid registers grid0 - grid7 with eight bits each represents a block map of the grid of 8x8 blocks. Each bit of the Grid registers represents one rectangular (gridX)x(gridY) block of pixels which covers the LCD screen display area. Within these registers, a 0 selects Pattern 0 (defined below) and a 1 selects Pattern 1. All cells have the same size, defined by one horizontal and one vertical grid block size registers gridX and gridY. When the programmed block size is such that the complete 8x8 grid is larger than the total screen area, only the blocks or part of blocks that are included in the output screen space are rendered. The 8x8 block set is upper left justified, such that all blocks on the right and bottom sides that are outside of the total display area are not rendered.
54/89
ADE3700
Pattern Generator
When the programmed block size is such that the complete 8x8 grid is smaller than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black.
Figure 7: Pattern Generator (Screen Split)
2.13.2 Pattern Engine
In order to display two patterns simultaneously on the LCD screen, the Pattern Generator has two pattern display engines. Each engine can display horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color scales. It is also possible to select the video stream from the scaler as a pattern. The pattern engine displays a bi-directional x-y symmetric pattern. Two 24-bit colors, C0 and C1, are alternately displayed with a horizontal period of Width and vertical period of Height. Programming a large Width and a small Height generates horizontal bars whereas the opposite will generate vertical bars. Programming small numbers for Width and Height generates checker patterns. Each of the two patterns is also given X and Y offset attributes, so that it is possible to center the pattern inside the grid blocks. A gradient effect can be applied independently on each of the two patterns, to either or both horizontal and vertical directions. The gradient effect takes two parameters: STEP and DELTA that define a ramp.
2.13.3 Borders
The Border Generator adds a single pixel width border to the whole display area. Each of the four sides of the display can be one of 8 independent colors.
Table 19: PGEN Registers (Sheet 1 of 5) Register Name
PGEN_PGEN_ENAB
Addr
0x0600
Mode
Bits
[7:1]
Default
Reserved 0x0 0x0 0x0 0x0
Description
R/W PGEN_GRID0 PGEN_GRID1 PGEN_GRID2 0x0601 0x0602 0x0603 R/W R/W R/W
[0] [7:0] [7:0] [7:0]
0 = disable PGEN block 1 = enable PGEN block Grid Row 0 Grid Row 1 Grid Row 2
55/89
Pattern Generator
Table 19: PGEN Registers (Sheet 2 of 5) Register Name
PGEN_GRID3 PGEN_GRID4 PGEN_GRID5 PGEN_GRID6 PGEN_GRID7 PGEN_GRID_X_L PGEN_GRID_X_H
ADE3700
Addr
0x0604 0x0605 0x0606 0x0607 0x0608 0x0609 0x060A
Mode
R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:4]
Default
0x0 0x0 0x0 0x0 0x0 0x0 Grid Row 3 Grid Row 4 Grid Row 5 Grid Row 6 Grid Row 7
Description
width of a grid block in pixels [7:0] Reserved
R/W PGEN_GRID_Y_L PGEN_GRID_Y_H 0x060B 0x060C R/W PGEN_GRID_X_OFFSET_X_L PGEN_GRID_X_OFFSET_X_H 0x060D 0x060E R/W PGEN_GRID_Y_OFFSET_Y_L PGEN_GRID_Y_OFFSET_Y_H PGEN_P0_MODE 0x060F 0x0610 0x0611 R/W R/W R/W R/W R/W R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:4] [3:0]
0x0 0x0
width of a grid block in pixels [11:8] height of a grid block in pixels [7:0] Reserved
0x0 0x0
height of a grid block in pixels [11:8] grid block horizontal offset in pixels [7:0] Reserved
0x0 0x0
Grid Block Horizontal Offset in pixels [11:8] Grid Block Vertical Offset in pixels
Pattern 0 Control [7:5] [4:2] [1] 0x0 0x0 0x0 number of bars in C0 number of bars in C1 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart 0: normal mode 1: C0 = video bypass Pattern 1 Control
R/W PGEN_P1_MODE 0x0612 R/W R/W R/W
[0]
0x0
[7:5] [4:2] [1]
0x0 0x0 0x0
number of bars in C0 number of bars in C1 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart 0: normal mode 1: C0 = video bypass Pattern 0 Bar Width [7:0] Reserved
R/W PGEN_P0_WIDTH_X_L PGEN_P0_WIDTH_X_H 0x0613 0x0614 R/W PGEN_P0_WIDTH_X_OFFSET_L 0x0615 R/W R/W
[0] [7:0] [7:4] [3:0] [7:0]
0x0 0x0
0x0 0x0
Pattern 0 Bar Width [11:8] Pattern 0 Horizontal Offset [7:0]
56/89
ADE3700
Table 19: PGEN Registers (Sheet 3 of 5) Register Name
PGEN_P0_WIDTH_X_OFFSET_H
Pattern Generator
Addr
0x0616
Mode
Bits
[7:4]
Default
Reserved 0x0 0x0 0x0 0x0 0x0
Description
R/W PGEN_P0_HEIGHT_Y_L PGEN_P0_HEIGHT_Y_H 0x0617 0x0618 R/W R/W R/W PGEN_P0_HEIGHT_Y_OFFSET_L PGEN_P0_HEIGHT_Y_OFFSET_H 0x0619 0x061A R/W PGEN_P1_WIDTH_X_L PGEN_P1_WIDTH_X_H 0x061B 0x061C R/W PGEN_P1_WIDTH_X_OFFSET_L PGEN_P1_WIDTH_X_OFFSET_H 0x061D 0x061E R/W PGEN_P1_HEIGHT_Y_L PGEN_P1_HEIGHT_Y_H 0x061F 0x0620 R/W R/W R/W PGEN_P1_HEIGHT_Y_OFFSET_L PGEN_P1_HEIGHT_Y_OFFSET_H 0x0621 0x0622 R/W PGEN_P0_COLOR_R_C0 PGEN_P0_COLOR_G_C0 PGEN_P0_COLOR_B_C0 PGEN_P0_COLOR_R_C1 PGEN_P0_COLOR_G_C1 PGEN_P0_COLOR_B_C1 PGEN_P1_COLOR_R_C0 PGEN_P1_COLOR_G_C0 PGEN_P1_COLOR_B_C0 PGEN_P1_COLOR_R_C1 PGEN_P1_COLOR_G_C1 PGEN_P1_COLOR_B_C1 PGEN_P0_GRADDELTA_R PGEN_P0_GRADDELTA_G PGEN_P0_GRADDELTA_B 0x0623 0x0624 0x0625 0x0626 0x0627 0x0628 0x0629 0x062A 0x062B 0x062C 0x062D 0x062E 0x062F 0x0630 0x0631 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Pattern 0 Horizontal Offset [11:8] Pattern 0 Bar Height [7:0] Pattern 0 Vertical Sequence Increment Pattern 0 Bar Height [11:8] Pattern 0 Vertical Offset [7:0] Reserved
0x0 0x0
Pattern 0 Vertical Offset [11:8] Pattern 1 Bar Width [7:0] Reserved
0x0 0x0
Pattern 1 Bar Width [11:8] Pattern 1 Horizontal Offset [7:0] Reserved
0x0 0x0 0x0 0x0 0x0
Pattern 1 Horizontal Offset [11:8] Pattern 1 Bar Height [7:0] Pattern 1 Vertical Sequence Increment Pattern 1 Bar Height [11:8] Pattern 1 Vertical Offset [7:0] Reserved
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Pattern 1 Vertical Offset [11:8] Pattern 0 Color C0 - Red Pattern 0 Color C0 - Green Pattern 0 Color C0 - Blue Pattern 0 Color C1 - Red Pattern 0 Color C1 - Green Pattern 0 Color C1 - Blue Pattern 1 Color C0 - Red Pattern 1 Color C0 - Green Pattern 1 Color C0 - Blue Pattern 1 Color C1 - Red Pattern 1 Color C1 - Green Pattern 1 Color C1 - Blue Pattern 0 Gradient Delta On Red Pattern 0 Gradient Delta On Green Pattern 0 Gradient Delta On Blue
57/89
Pattern Generator
Table 19: PGEN Registers (Sheet 4 of 5) Register Name
PGEN_P0_GRADSTEP_X PGEN_P0_GRADSTEP_Y PGEN_P1_GRADDELTA_R PGEN_P1_GRADDELTA_G PGEN_P1_GRADDELTA_B PGEN_P1_GRADSTEP_X PGEN_P1_GRADSTEP_Y PGEN_P0_SEQ_COL0_COL1
ADE3700
Addr
0x0632 0x0633 0x0634 0x0635 0x0636 0x0637 0x0638 0x0639
Mode
R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Pattern 0 Gradient Horizontal Step Pattern 0 Gradient Vertical Step Pattern 1 Gradient Delta On Red Pattern 1 Gradient Delta On Green Pattern 1 Gradient Delta On Blue Pattern 1 Gradient Horizontal Step Pattern 1 Gradient Vertical Step Reserved
R/W
[6:4] [3]
0x0
Pattern 0 Bar 1 Color Reserved
R/W PGEN_P0_SEQ_COL2_COL3 0x063A R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 0 Bar 0 Color Reserved
0x0
Pattern 0 Bar 3 Color Reserved
R/W PGEN_P0_SEQ_COL4_COL5 0x063B R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 0 Bar 2 Color Reserved
0x0
Pattern 0 Bar 5 Color Reserved
R/W PGEN_P0_SEQ_COL6_COL7 0x063C R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 0 Bar 4 Color Reserved
0x0
Pattern 0 Bar 7 Color Reserved
R/W PGEN_P1_SEQ_COL0_COL1 0x063D R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 0 Bar 6 Color Reserved
0x0
Pattern 1 Bar 1 Color Reserved
R/W PGEN_P1_SEQ_COL2_COL3 0x063E R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 1 Bar 0 Color Reserved
0x0
Pattern 1 Bar 3 Color Reserved
R/W PGEN_P1_SEQ_COL4_COL5 0x063F R/W
[2:0] [7] [6:4] [3]
0x0
Pattern 1 Bar 2 Color Reserved
0x0
Pattern 1 Bar 5 Color Reserved
R/W
[2:0]
0x0
Pattern 1 Bar 4 Color
58/89
ADE3700
Table 19: PGEN Registers (Sheet 5 of 5) Register Name
PGEN_P1_SEQ_COL6_COL7
Pattern Generator
Addr
0x0640
Mode
Bits
[7]
Default
Reserved 0x0
Description
R/W
[6:4] [3]
Pattern 1 Bar 7 Color Reserved
R/W PGEN_B_TOP_BOTTOM 0x0641 R/W R/W R/W R/W R/W R/W R/W R/W PGEN_B_LEFT_RIGHT 0x0642 R/W R/W R/W R/W R/W R/W R/W R/W PGEN_X_TOTAL_L PGEN_X_TOTAL_H 0x0643 0x0644 R/W PGEN_Y_TOTAL_L PGEN_Y_TOTAL_H 0x0645 0x0646 R/W R/W R/W
[2:0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Pattern 1 Bar 6 Color Top Border Enable Top Border Red; 0 = Off, 1= On Top Border Green; 0 = Off, 1= On Top Border Blue; 0 = Off, 1= On Bottom Border Enable Bottom Border Red; 0 = Off, 1= On Bottom Border Green; 0 = Off, 1= On Bottom Border Blue; 0 = Off, 1= On Left Border Enable Left Border Red; 0 = Off, 1= On Left Border Green; 0 = Off, 1= On Left Border Blue; 0 = Off, 1= On Right Border Enable Right Border Red; 0 = Off, 1= On Right Border Green; 0 = Off, 1= On Right Border Blue; 0 = Off, 1= On Total Horizontal Size [7:0] Reserved
0x0 0x0
Total Horizontal Size [11:8] Total Vertical Size [7:0] Reserved
0x0
Total Vertical Size [11:8]
59/89
sRGB
ADE3700
2.14
sRGB
The sRGB block performs two primary functions: 1. Parametric gamma correction on multiple windows or full screen, used for video enhancement in a window and digital contrast/brightness control. The window coordinates are set by TCON registers. 2. 3D color cube warping RGB color space.
2.14.1 Parametric Gamma, Digital Contrast / Brightness on Multiple Windows
The function can be applied to the entire window by programming the window control to full screen. Each color channel acts independently. Simple digital contrast and brightness can be programmed using this hardware function. The desired window coordinates are programmed into the TCON.
2.14.2 Color Space Warp
The 8 corners of the color cube are independently controlled in 3D space with smooth interpolation of intermediate colors. Registers are 2's complement color delta's. For example, to make WHITE more like RED, program SRGB_WHITE_R to a small positive value.
Figure 8: Color Space Warp
Color Space Warp
IN
OUT
Table 20: sRGB Registers (Sheet 1 of 3) Register Name
SRGB_CTRL
Addr
0x0D00
Mode
R/W R/W
Bits
[7:6] [5:4]
Default
0x0 0x0 Reserved
Description
gamma_b control 0x0: disable 0x1: full screen 0x2: windowed 0x3: Reserved
R/W
[3:2]
0x0
gamma_a control 0x0: disable 0x1: full screen 0x2: windowed 0x3: Reserved
R/W
[1:0]
0x0
sRGB control 0x0: disabled 0x1: full screen 0x2: windowed 0x3: Reserved
SRGB_BLACK_R
0x0D01
R/W
[7:0]
0x0
Black Point Red Delta
60/89
ADE3700
Table 20: sRGB Registers (Sheet 2 of 3) Register Name
SRGB_BLACK_G SRGB_BLACK_B SRGB_RED_R SRGB_RED_G SRGB_RED_B SRGB_GREEN_R SRGB_GREEN_G SRGB_GREEN_B SRGB_BLUE_R SRGB_BLUE_G SRGB_BLUE_B SRGB_YELLOW_R SRGB_YELLOW_G SRGB_YELLOW_B SRGB_CYAN_R SRGB_CYAN_G SRGB_CYAN_B SRGB_MAGENTA_R SRGB_MAGENTA_G SRGB_MAGENTA_B SRGB_WHITE_R SRGB_WHITE_G SRGB_WHITE_B SRGB_GAMMA_A_RED_A SRGB_GAMMA_A_RED_B SRGB_GAMMA_A_RED_C SRGB_GAMMA_A_GREEN_A SRGB_GAMMA_A_GREEN_B SRGB_GAMMA_A_GREEN_C SRGB_GAMMA_A_BLUE_A SRGB_GAMMA_A_BLUE_B SRGB_GAMMA_A_BLUE_C SRGB_GAMMA_B_RED_A SRGB_GAMMA_B_RED_B SRGB_GAMMA_B_RED_C
sRGB
Addr
0x0D02 0x0D03 0x0D04 0x0D05 0x0D06 0x0D07 0x0D08 0x0D09 0x0D0A 0x0D0B 0x0D0C 0x0D0D 0x0D0E 0x0D0F 0x0D10 0x0D11 0x0D12 0x0D13 0x0D14 0x0D15 0x0D16 0x0D17 0x0D18 0x0D19 0x0D1A 0x0D1B 0x0D1C 0x0D1D 0x0D1E 0x0D1F 0x0D20 0x0D21 0x0D22 0x0D23 0x0D24
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Black Point Green Delta Black Point Blue Delta Red Point Red Delta Red Point Green Delta Red Point Blue Delta Green Point Red Delta Green Point Green Delta Green Point Blue Delta Blue Point Red Delta Blue Point Green Delta Blue Point Blue Delta Yellow Point Red Delta Yellow Point Green Delta Yellow Point Blue Delta Cyan Point Red Delta Cyan Point Green Delta Cyan Point Blue Delta Magenta Point Red Delta Magenta Point Green Delta Magenta Point Blue Delta White Point Red Delta White Point Green Delta White Point Blue Delta Parametric A Gamma A Red, Gamma Parametric A Gamma B Red, Contrast Parametric A Gamma C Red, Brightness Parametric A Gamma A Green, Gamma Parametric A Gamma B Green, Contrast Parametric A Gamma C Green, Brightness Parametric A Gamma A Blue, Gamma Parametric A Gamma B Blue, Contrast Parametric A Gamma C Blue, Brightness Parametric B Gamma A Red, Gamma Parametric Gamma B Red, Contrast Parametric Gamma C Red, Brightness
61/89
On-Screen Display (OSD)
Table 20: sRGB Registers (Sheet 3 of 3) Register Name
SRGB_GAMMA_B_GREEN_A SRGB_GAMMA_B_GREEN_B SRGB_GAMMA_B_GREEN_C SRGB_GAMMA_B_BLUE_A SRGB_GAMMA_B_BLUE_B SRGB_GAMMA_B_BLUE_C
ADE3700
Addr
0x0D25 0x0D26 0x0D27 0x0D28 0x0D29 0x0D2A
Mode
R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0
Description
Parametric Gamma A Green, Gamma Parametric Gamma B Green, Contrast Parametric Gamma C Green, Brightness Parametric Gamma A Blue, Gamma Parametric Gamma B Blue, Contrast Parametric Gamma C Blue, Brightness
2.15
On-Screen Display (OSD)
The integrated On-Screen Display (OSD) controller is a character-based overlay with a high level of features and over 100 kbits of on-board dedicated RAM storage.
q q q q q q q q q q q
15 row by 30 column character-mapped display Four user-definable windows 12x18-pixel characters with optional horizontal and vertical doubling on a row-by-row basis Two 16-entry 24-bit RGB user-definable color maps 192 RAM-based monochrome 1 bpp characters 64 RAM-based graphics 4 bpp characters Text character attributes: foreground/background color, blinking Graphics character attributes: per-pixel color, vertical/horizontal mirroring Row attributes: double width, double height Window attributes: window visibility, position, size, border shadow, color table Global attributes: OSD visibility, OSD screen position, alpha fade in/fade out, global size doubling, rotation in ninety-degree increments Single-bit enable/disable
q
For information on OSD programming, see the OSD Programming Manual.
2.15.1 OSD Access via I2C
The OSD uses a dedicated memory space that is accessed through an I2C port. The data stream sent to the OSD register starts with two header bytes. These specify the type of transfer and the row/column position for screen map transfers, the character index for font definition transfers, or the color index for color map transfers. A stream of OSD writes to the OSD I2C register can fill in a segment of the OSD memory space with an internal auto-incrementing index register. The protocol is as follows: 1. Issue a start sequence with the R/W bit set to W. 2. Write to the OSD register. The first byte transferred is the index of the first internal OSD register to be written. The next byte contains the data to be written to that register. Subsequent bytes are written to successive internal OSD registers. 3. Continue writing data bytes until the desired range of OSD internal registers has been written (the ADE3700 device will issue an ACK on each transfer). 4. Issue an I2C stop sequence.
62/89
ADE3700
Character Display
On-Screen Display (OSD)
There are two 96-character monochrome fonts and two 32-character four-bit color fonts, a total of 256 characters. The four bits of color are an index into one of two 16 entry color lookup tables. Entries in the color lookup table specify a 24-bit RGB color. All fonts and the color look-up table are RAM-based and must be downloaded to the OSD's internal RAM before use. Font addressing is as follows: character indexes 0x00-0x1F refer to color font 0, 0x20-0x7F refer to monochrome font 0, 0x80-0x9F refer to color font 1 and 0xA0-0xFF refer to monochrome font 1. Screen Map The OSD uses a character map of 15 rows x 30 columns. Each character occupies one byte. The value of each byte indicates the character to display. The OSD character map is addressed by specifying the row and column as part of the data transfer. Attribute Map The attribute map is defined as 16 rows by 31 columns. It has an extra row and an extra column compared to the screen map.
Figure 9: Character Attribute Map
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04
Row Attributes
05 06 07 08 09 10 11 12 13 14 15
Character Attributes
wa wa = window attributes ga = global attributes
ga
wa
ga
wa
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
The values corresponding to printable row/column addresses provide character attributes. Each character on the screen has an attribute byte specifying (in the case of monochrome fonts) three bits of background color, four bits of foreground color, and a blink on/off bit. Blinking, when enabled, has a period of 100 frames (50 frames on, 50 frames off). Column 31 of each row contains row attributes. These include the fourth bit of the background color and two bits controlling double-height and double-width text. Row 15 contains global attributes, including vertical and horizontal OSD position on the screen, alpha blending, shadow/bordering, OSD rotation, color map selection, and normal/double size. Alpha blending allows the OSD display to be mixed with the incoming video signal for transparency
63/89
On-Screen Display (OSD)
ADE3700
effects. An alpha value of 255 makes the OSD opaque, while a value of 0 makes the OSD invisible, with a linear ramp of transparency between these two endpoints. Separate registers control alpha for foreground and background pixels. A fade-in/fade-out feature ramps the alpha values every six frames, starting from their current value and going up or down the sequence: 0, 16, 32, 64, 128, 192, 224, 240, 255. Row 15 also contains definitions for the four display windows. These windows define regions on the screen to which borders and shadows can be applied. (They are not analogous to windows in a GUI display, in that they do not represent four independent data displays. There is only one character map. The windows essentially define an area around which a border can be drawn or to which attributes can be assigned.) Windows also determine which of the two color tables will be used for the characters inside. Windows have a fixed precedence: Window 0 has the highest precedence and Window 3 the lowest. When windows overlap, the precedence determines which borders will be displayed and which color tables will be used in the overlapping area. Monochrome and color fonts are affected differently by attribute bytes. Monochrome characters are affected by shadows and borders, and have their color specified by the foreground/background attributes. Color characters interpret the attribute byte differently than monochrome characters, using it to define blinking and 90-degree rotations rather than blinking, foreground color, and background color. Color Tables There are two color tables, each containing sixteen entries by three bytes each, giving a 24-bit RGB value for each entry. Entry 0 is used for the shadow color for monochrome characters and borders. Color-table selection is made on a window-by-window basis. When writing the color table, the "row" value in the first header byte is interpreted as the color table index, while the "column" value in the second header byte encoded to select the color table (0 or 1) and the primary color (red, green, or blue). The data byte following the second header byte is written to the selected (table, index, primary) location. Font Data Font data is sent to the OSD through burst transfers. The first header byte selects the transfer type and provides three bits of the character index, while the second header byte selects transfer type "C" and gives the remaining five bits of offset. The data bytes for the character follow, given from top to bottom and left to right in the character cell. A monochrome character is 27 bytes long, with two scan-lines occupying three bytes. A color character is four times as long as a monochrome character (108 bytes), with each byte containing two four-bit pixels. Both color and monochrome fonts are 12 pixels wide and 18 high. Transfer Formats The transfer format consists of two header bytes and a variable number of data bytes. The header bytes determine the type of transfer (character, attribute, monochrome font, color font, or color table). Addressing is by row and column in the case of character or attribute transfers, and by character index in the case of font transfers. When writing to the color table, the "column" field determines the color table and R/G/B selection.
64/89
ADE3700
On-Screen Display (OSD)
Table 21: OSD Access Header Definition
Header Byte First Bits [7:4] Description Type of data transfer. Valid values are: 0x8: screen map 0x9: color LUT 0xA: attribute map 0xC: font data all others: Reserved [3:0] For screen map or attribute map access, this is the row index. For color LUT access, this is the color index. For font data access, bits [2:0] are the MSB's of the character index. Second [7:6] Type of data burst: 0x0: A/B modes: Only one data byte follows this header byte. 0x1: C mode: All bytes following this header byte are data bytes until the serial interface indicates an end-of-transmission. The OSD internally auto-increments after each byte. In screen and attribute map access modes the column number is incremented after each byte, wrapping to the beginning of the next row once column 29 is passed and wrapping to row 0 if row 14 is passed. Either mode may be used for display and character attribute modes, except for the off-screen attributes in column 15 and row 30, which must use mode A/B. Font definition mode must use mode C. [5] [4:0] must be set to zero In screen and attribute map access modes, this is the column number. In font data access mode, this gives the 5 lsb's of the character index. In color LUT access mode, it selects the table number and color to be written: 0x0: LUT 0, red 0x1: LUT 0, green 0x2: LUT 0, blue 0x3: LUT 1, red 0x4: LUT 1, green 0x5: LUT 1, blue 0x6 - 0x7: Reserved
Table 22: OSD Attribute Map Definition (Sheet 1 of 4) Row
15 15
Column
12 13
Bits
[7:0] [7:0]
Description
Vertical OSD position / 4 Horizontal OSD position / 5
65/89
On-Screen Display (OSD)
Table 22: OSD Attribute Map Definition (Sheet 2 of 4) Row
15
ADE3700
Column
15
Bits
[7] [6:5] 0: OSD off 1: OSD on
Description
0x0: plain characters 0x1: border characters 0x2: shadow characters 0x3: Reserved Reserved 0: normal 1: flip OSD 0: fade off 1: fade on 0: normal size 1: double size Foreground Alpha Blending Background Alpha Blending Window 0 Row Start Window 0 Row End Window 1 Row Start Window 1 Row End Window 2 Row Start Window 2 Row End Window 3 Row Start Window 3 Row End Window 0 Column Start Window 0 Visibility 0: Off 1: On
[4:3] [2] [1] [0] 15 15 15 19 20 0 [7:0] [7:0] [7:4] [3:0] 15 3 [7:4] [3:0] 15 6 [7:4] [3:0] 15 9 [7:4] [3:0] 15 1 [7:3] [2]
[1] [0] 15 4 [7:3] [2]
Reserved Window 0 Shadow Enable Window 1 Column Start Window 1 Visibility 0: Off 1: On
[1] [0]
Reserved Window 1 Shadow Enable
66/89
ADE3700
On-Screen Display (OSD)
Table 22: OSD Attribute Map Definition (Sheet 3 of 4) Row
15
Column
7
Bits
[7:3] [2]
Description
Window 2 Column Start Window 2 Visibility 0: Off 1: On
[1] [0] 15 10 [7:3] [2]
Reserved Window 2 Shadow Enable Window 3 Column Start Window 3 Visibility 0: Off 1: On
[1] [0] 15 2 [7:3] [2:0] 15 5 [7:3] [2:0] 15 8 [7:3] [2:0] 15 11 [7:3] [2:0] 15 16 [7:6] [5:4] [3:2] [1:0] 15 17 [7:6] [5:4] [3:2] [1:0] 15 21 [7:4] [3] [2] [1] [0]
Reserved Window 3 Shadow Enable Window 0 Column End Reserved Window 1 Column End Reserved Window 2 Column End Reserved Window 3 Column End Reserved Window 3 Shadow Width Window 2 Shadow Width Window 1 Shadow Width Window 0 Shadow Width Window 3 Shadow Height Window 2 Shadow Height Window 1 Shadow Height Window 0 Shadow Height Reserved window 3 color LUT select window 2color LUT select window 1 color LUT select window 0 color LUT select
67/89
Flicker
Table 22: OSD Attribute Map Definition (Sheet 4 of 4) Row
0 to 14
ADE3700
Column
30
Bits
[7:3] [2] [1] [0] Reserved
Description
MSB of background color for the row double high enable for the row double wide enable for the row 3 LSBs of background color for 1bpp chars no function for 4bpp color chars
0 to 14
0 to 29
[7:5]
[4] [3:0]
blink enable foreground color for 1bpp chars for 4bpp color chars [3:2]: Reserved [1]: flip vertical [0]: flip horizontal
Table 23: OSD Register Register Name
OSD_PORT
Addr
0x0C02
Mode
R/W
Bits
[7:0]
Default (hex)
0
Description
OSD Access Port
2.16
Flicker
The Flicker block computes correlations of the image data with potential inversion patterns of the LCD which in turn allows the microcontroller to modify the polarity signal to cancel large areas of flicker. This function is only useful in SmartPanel applications. The incoming image is scored against 8 vertical Walsh functions. All patterns are considered vertically, while horizontally the pixels are assumed to be alternating RGB components. The scores (0 to 7) are 32-bit unsigned quantities that reflect the correlation of the programmed window area with the 8 Walsh functions. The horizontal inversion of the LCD drivers must be programmed into FLICKER_CTRL0[2:0]. The most common setting is +-+ or -+- (RGB). A calculation is completed after the number of frames programmed into the FRAME_CNT_MAX register (0xCA03). With each frame the calculation is performed on only a vertical strip. The width of that strip (in pixels) is determined by the value programmed in the HBLOCK_SIZE register (0xCA02) with the following relation: strip width = 2 ^ (3 + HBLOCK_SIZE). The free_run/freeze_scores bit (FLICKER_CTRL0[4]) enables the final calculation to be captured easily by the MCU. The internal flicker calculation continues to run -- only the update of the I2C registers is blocked when this bit is set to prevent corruption during readout.
68/89
ADE3700
Refer to the Flicker Programming Guide for more details.
Table 24: Flicker Registers (Sheet 1 of 2) Register Name
FLK_CTRL
Flicker
Addr
0x0CA1
Mode
R/W R/W R/W
Bits
[7:6] [5] [4]
Default
0x0 0x1 0x0 Reserved
Description
0: straight line uniform function 1: straight line hill function (normal) 0: free-running 1: freeze scores Set to a 1 when the microcontroller is reading multibyte scores to prevent update corruption. horizontal subpixel polarity inversion pattern of LCD (even/odd pixels) 0x0: -R-G-B / +R+G+B 0x1: -R-G+B / +R+G-B 0x2: -R+G-B / +R-G+B (Default) 0x3: -R+G+B / +R-G-B 0x4: +R-G-B / -R+G+B 0x5: +R-G+B / -R+G-B 0x6: +R+G-B / -R-G+B 0x7: +R+G+B / -R-G-B
R/W
[2:0]
0x5
FLK_HBLOCK_SIZE
0x0CA2
R/W
[7:4] [3:0] [7:0]
0x0
Reserved width in pixels of the per frame scored area = 2 ^ (3+ hblock_size) number of frames to complete one measurement total number of pixels in a line is: frame_cnt_max * (2 ^ (3+hblock_size)) example: hblock_size = 4; frame_cnt_max = 8; In each frame only one portion of the image is being scored. The width of that portion is 2 ^ (3 + hblock_size) = 128 pixels and the height is the full height of the image. Thus the total scored area after 8 frames is 128*8 = 1024 pixels wide.
FLK_FRAME_CNT_MAX
0x0CA3
R/W
0x8
FLK_MEAS0_0 FLK_MEAS0_1 FLK_MEAS0_2 FLK_MEAS0_3 FLK_MEAS1_0 FLK_MEAS1_1 FLK_MEAS1_2 FLK_MEAS1_3 FLK_MEAS2_0 FLK_MEAS2_1 FLK_MEAS2_2
0x0CB1 0x0CB2 0x0CB3 0x0CB4 0x0CB5 0x0CB6 0x0CB7 0x0CB8 0x0CB9 0x0CBA 0x0CBB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0
Score for Pattern 0
0x0
Score for Pattern 1
00x
Score for Pattern 2
69/89
Gamma
Table 24: Flicker Registers (Sheet 2 of 2) Register Name
FLK_MEAS2_3 FLK_MEAS3_0 FLK_MEAS3_1 FLK_MEAS3_2 FLK_MEAS3_3 FLK_MEAS4_0 FLK_MEAS4_1 FLK_MEAS4_2 FLK_MEAS4_3 FLK_MEAS5_0 FLK_MEAS5_1 FLK_MEAS5_2 FLK_MEAS5_3 FLK_MEAS6_1 FLK_MEAS6_2 FLK_MEAS6_3 FLK_MEAS6_4 FLK_MEAS7_0 FLK_MEAS7_1 FLK_MEAS7_2 FLK_MEAS7_3
ADE3700
Addr
0x0CBC 0x0CBD 0x0CBE 0x0CBF 0x0CC0 0x0CC1 0x0CC2 0x0CC3 0x0CC4 0x0CC5 0x0CC6 0x0CC7 0x0CC8 0x0CC9 0x0CCA 0x0CCB 0x0CCC 0x0CCD 0x0CCE 0x0CCF 0x0CD0
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
Description
0x0
Score for Pattern 3
0x0
Score for Pattern 4
0x0
Score for Pattern 5
0x0
Score for Pattern 6
0x0
Score for Pattern 7
2.17
Gamma
The Gamma block performs an 8-bit to 10-bit lookup table on the 3 x 8 bits (R, G, B) color data coming from the LCD Scaler. The lookup table (LUT RAM) contains the corresponding 10-bit output corrected color for each 8-bit input color. The RAMs are individually programmable (read and write) using I2C access. The memory map is as follows: I2C address 0x1000 to 0x11FF: Red RAM I2C address 0x1200 to 0x13FF: Green RAM I2C address 0x1400 to 0x15FF: Blue RAM Even addresses are the 8-bit LSBs of the 10-bit gamma value. Odd addresses are the 2 MSBs.
70/89
ADE3700
APC
Table 25: Gamma Registers Register Name
GAMMA_CTRL
Addr
0x0C10
Mode
R/W
Bits
[7:4] [3] [2] [1:0]
Default
0x0 0x0 0x0 0x0 Reserved
Description
0: normal 1: disable RAM access 0: normal 1: test mode Gamma Mode Select 0x0: 10-bit linear bypass 0x1: 8-bit->10-bit gamma table (normal) 0x2: 8-bit linear bypass (no interpolation) 0x3: 8-bit->10-bit gamma table (normal)
2.18
APC
APC (formerly known as Arithmos Perfect Color) dithers an input 10 bit video stream down to 4-8 output bits. The dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as:
q q q q
Fixed dither patterns Contours Flickering pixels Phase correlated flickering, which creates wave patterns known as "swimming"
Table 26: APC Registers
Register Name
APC_APC0
Addr
0x0C20
Mode
Bits
[7]
Default
Reserved 0x0 0x0
Description
R/W R/W
[6:5] [4:1]
Frame Modulation Period - 1 0x0 - 0x3: 8-bit out 0x4: 4b out 0x5: 5b out 0x6: 6b out 0x7: 7b out 0x8: 8-bit out 0: normal 1: disable APC -- truncate LSBs Reserved
R/W APC_APC1 0x0C21 R/W R/W
[0] [7:2] [1] [0]
0x0
0x0 0x0
Offset the phase LUT Offset the dither LUT
71/89
Output Multiplexer
ADE3700
2.19
Output Multiplexer
The Output Multiplexer formats the single wide data stream from the output of the APC block into a single or double wide data path for the flat panel. The architecture is shown in Figure 10.
Figure 10: Output Mux Block Diagram
rin[7:0]
8
Right Shift
8
Byte Flip
8
gin[7:0]
8
Right Shift
8
Byte Flip
8
Red & Blue Swap
24
Single to Double Wide Converter
FLOPS
48
Data Inversion
bin[7:0]
8
Right Shift
8
Byte Flip
8 hclk
48 rda[7:0] gda[7:0] bda[7:0] rdb[7:0] gdb[7:0] bdb[7:0]
2 inv_a inv_b
enab_in hsync_in vsync_in tcon_in[13:0] pwm_a_in pwm_b_in
14 2
tci[13:0] Output Mux/Reg FLOPS RSDS Logic and Per Pin Delay 8 48 3
tcon_out[7:0]
routa[7:0] gouta[7:0] bouta[7:0] routb[7:0] goutb[7:0] boutb[7:0]
enab_out clk_out hsync_out vsync_out
Latency is not important, as long as the timing relationship between hsync, vsync, enab and data is preserved at the output. In Double Wide mode, the first pixel must be properly aligned even if the number of pixels in blanking or active are odd. The divide-by-2 circuit can be set to resync per line (based on data_enab and hsync_in edge) and per frame (based on vsync_in edge). The most reliable timing is when hsync and vsync are in the "low" counts of the timing core counters (i.e. hsync_set and hsync_rst are both below the active data region start/end counts). In the event that hsync and vsync are in the "high" (after active region) counts, the device should be set to sync to data_enab_re. The Per Pin Delay and RSDS logic occur after the last latch and are implemented on all channels to maintain delay balance between signals that go into RSDS mode (data and clk/hsync) and those that do not (de/vsync and tcon).
72/89
ADE3700 2.19.1 Sub Block Function
2.19.1.1 Right Shift
q q
Output Multiplexer
shifts right from 0 to 4 positions, fills from the top with zeroes out_mux_ctrl1[2:0]
2.19.1.2 Byte Flip
q q
flips data bits in a byte from LSB to MSB, i.e. out[7:0] = in[0:7] out_mux_ctrl0[4]
2.19.1.3 Red & Blue Swap
q q
swaps red and blue channels, i.e. out[23:0] = {in[7:0],in[15:8],in[23:16]} out_mux_ctrl0[3]
2.19.1.4 Single to Double Wide Converter
q
in Single Wide mode (out_mux_ctrl0[1] = 0) -- flops all data into either A or B channels depending on out_mux_ctrl0[2] -- either inv_a or inv_b is active depending on active channel
q
in Double Wide mode (out_mux_ctrl0[1] = 1) -- flops data into A/B or B/A positions depending on out_mux_ctrl0[2]. -- divides clock by 2 (hclk = half speed DCLK), resyncing each line with data enable -- output data transitions as posedge/negedge as set in out_mux_ctrl0[5] -- can handle odd output htotal (i.e. all divide by 2's and state machines must be resynced per line)
2.19.1.5 Data Inversion
q q q
resyncs at the end of each line to inactive state with data enable falling edge - invert is possible on the first pixel - compares 1st pixel to blanking value compares subsequent 24-bit/48-bit data to the last output; if more bits flip (i.e. hamming distance > active_bit_width/2), invert data word and toggle invert pin counts only active bits in hamming distance as determined by right shift and bit flip settings; zeroes out non active data signals at output controls: -- out_mux_ctrl1[4] - A and B channels have separate independent - A and B channels treated as one 48-bit channel, inv_a = inv_b -- out_mux_ctrl1[5] - data invert output polarity -- out_mux_ctrl1[6] - data invert enable
q
q
q
data invert pins can also be driven by tcon srtd[26] and srtd[27] for panel balancing (out_mux_ctrl2[6] and out_mux_ctrl2[7]) data can be inverted at the front end of the data inversion detection using tcon signals, either separate or combined channels (out_mux_ctrl3[0])
q
2.19.1.6 Output Mux / Reg
q
combines all signals to form the desired outputs
73/89
Output Multiplexer
q q q
ADE3700
last point the data is flopped with DCLK before the pins gated clock available from tcon_srtd[12] in tcon mode see tables 2.2 - 2.5 for configurations.
Table 27: Output Mux Specification (Sheet 1 of 2)
Enable Data OUT_MUX_CTRL0[0] Enable TCON AB or BA Double Right Shift Byte Flip OUT_MUX_CTRL1[3] OUT_MUX_CTRL0[2] OUT_MUX_CTRL0[1] OUT_MUX_CTRL1[2:0] OUT_MUX_CTRL0[4]
0 0 X X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 X X X X 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 X 0 0 X X 1 1 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
1 X 1 0 X X 1 1
1 1 X 1 >0 0 1 1
1 1 X 1 >0 1 1 1
1 1 0 0 X X 0 X BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1
1 1 1 0 X X 0 X BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
1 1 X 1 0 X 0 X BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
1 1 X 1 >0 0 0 X BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
1 1 X 1 >0 1 0 X BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 GDA7 GDA6 GDA5 GDA4 GDA3 GDA2 GDA1 GDA0 RDA7 RDA6 RDA5 RDA4 RDA3 RDA2 RDA1
PWM enable OUT_MUX_CTRL3[1] PWM mux mode OUT_MUX_CTRL3[2] OBA7 OBA6 OBA5 OBA4 OBA3 OBA2 OBA1 OBA0 OGA7 OGA6 OGA5 OGA4 OGA3 OGA2 OGA1 OGA0 ORA7 ORA6 ORA5 ORA4 ORA3 ORA2 ORA1
BDA7 PWMA BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1
BDA0 PWMA BDA0
GDA7 GDA7 PWMB GDA7 GDA7 GDA7 GDA7 GDA7 GDA6 GDA6 GDA6 GDA6 GDA6 GDA6 GDA6 GDA6 GDA5 GDA5 GDA5 GDA5 GDA5 GDA5 GDA5 GDA5 GDA4 GDA4 GDA4 GDA4 GDA4 GDA4 GDA4 GDA4 GDA3 GDA3 GDA3 GDA3 GDA3 GDA3 GDA3 GDA3 GDA2 GDA2 GDA2 GDA2 GDA2 GDA2 GDA2 GDA2 GDA1 GDA1 GDA1 GDA1 GDA1 GDA1 GDA1 GDA1 GDA0 GDA0 GDA0 PWMB GDA0 GDA0 GDA0 GDA0 RDA7 RDA7 RDA7 RDA7 RDA7 RDA7 RDA7 TCI11 RDA6 RDA6 RDA6 RDA6 RDA6 RDA6 RDA6 RDA6 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA3 RDA3 RDA3 RDA3 RDA3 TCI11 RDA3 RDA3 RDA2 RDA2 RDA2 RDA2 RDA2 TCI10 RDA2 RDA2 RDA1 PWMA RDA1 RDA1 RDA1 TCI9 RDA1 RDA1
74/89
ADE3700
Table 27: Output Mux Specification (Sheet 2 of 2)
Output Multiplexer
ORA0 OBB7 OBB6 OBB5 OBB4 OBB3 OBB2 OBB1 OBB0 OGB7 OGB6 OGB5 OGB4 OGB3 OGB2 OGB1 OGB0 ORB7 ORB6 ORB5 ORB4 ORB3 ORB2 ORB1 ORB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDA0 PWMB RDA0 RDA0 RDA0 PWMA BDB7 PWMB BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0
TCI8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0
RDA0 RDA0 BDB7 TCI10 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 TCI9
TCI11 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 TCI10 GDB7 GDB6 GDB5 GDB4 GDB3 GDB2 GDB1 TCI9 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 TCI8
GDB7 GDB7 GDB7 GDB7 GDB7 GDB7 GDB7
GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 RDB7 RDB7 RDB7 RDB7 RDB7 RDB7 RDB7 TCI8
RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB3 RDB3 RDB3 RDB3 TCI11 RDB3 RDB3 RDB3 RDB2 RDB2 RDB2 RDB2 TCI10 RDB2 RDB2 RDB2 RDB1 RDB1 RDB1 RDB1 RDB0 RDB0 RDB0 RDB0 TCI9 TCI8 RDB1 RDB1 RDB1 RDB0 RDB0 RDB0
tci13 = tcon_in13, orb7 = output red B channel bit 7, rda3 = red A channel bit 3, etc. pwma = pwm_a input.
Table 28: CLK_OUT Mux Specification
enable data double clk invert
OUT_MUX_CTRL0[0] OUT_MUX_CTRL0[1] OUT_MUX_CTRL0[5] CLK_OUT
0 X X 0
1 0 0 DOTCLK
1 0 1 !DOTCLK
1 1 0 HCLK
1 1 1 !HCLK
75/89
Output Multiplexer
Table 29: Sync Mux Specification
ADE3700
enable data enable tcon
OUT_MUX_CTRL0[0] OUT_MUX_CTRL1[3]
0 0
1 0
1 1
ENAB_OUT HSYNC_OUT VSYNC_OUT
0 0 0
ENI HSI VSI
INV_A TCI_GATED_CLK INV_B
eni = enab_in, hsi = hsync_in, vsi = vsync_in.
Table 30: TCON Mux Specification
enable tcon enable PWM PWM mux mode
OUT_MUX_CTRL1[3] OUT_MUX_CTRL3[1] OUT_MUX_CTRL3[2]
X 0 X
X 1 0
0 1 1
TCON_OUT7 TCON_OUT6 TCON_OUT5 TCON_OUT4 TCON_OUT3 TCON_OUT2 TCON_OUT1 TCON_OUT0
TCI7 TCI6 TCI5 TCI4 TCI3 TCI2 TCI1 TCI0
TCI7 TCI6 TCI5 TCI4 TCI3 TCI2 PWM_A PWM_B
TCI7 TCI6 TCI5 TCI4 TCI3 TCI2 TCI1 TCI0
2.19.2 RSDS
In RSDS mode, clk and hsync outputs are the differential clock pair. All 48 data ports are combined into neighboring pairs (e.g. orb0 and orb1 are differential pairs in RSDS mode). the lower index is the positive sense differential output. TCON, data_enab and vsync outputs are unchanged. data_enab and vsync can be used to output LVCMOS data inversion signals independent of RSDS mode. The following table indicates the pin, timing and data relationships in RSDS mode.
Table 31: RSDS Mode Specifications RSDS Time
t t+1
clk_o
0 1
hsync_o
1 0
o[r,g,b][a,b](2n)
bit from 2n bit from 2n+1
o[r,g,b][a,b](2n+1)
!bit from 2n !bit from 2n+1
76/89
ADE3700
Table 31: RSDS Mode Specifications (Continued) RSDS Time
t+2 t+3
Output Multiplexer
clk_o
0 1
hsync_o
1 0
o[r,g,b][a,b](2n)
bit from 2n bit from 2n+1
o[r,g,b][a,b](2n+1)
!bit from 2n !bit from 2n+1
Note:
hsync_o is the positive clock signal according to the RSDS definition.
2.19.3 Per Pin Delay
Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to the XCLK period, which is assumed to be 37ns. Each pin can be delayed by up to 6ns in 0.4ns increments. Code 0x0 is the least delay, code 0xF is the maximum delay. The setting is accurate to 0.8ns across PVT. The calibration and resetting is done once per frame after the falling edge of vertical enable to prevent glitches from delay mux changes in the active data period. The delays are active in RSDS and normal output modes if enabled in the OUT_MUX_CTRL2 register.
Table 32: Output Mux Registers (Sheet 1 of 4) Register Name
OMUX_CTRL_0
Addr
0x0C30
Mode
R/W
Bits
[7]
Default
0x0
Description
in 2 ppc, 0: data invert for A+B comb. 1: data invert A/B separate 0x0 - 0x4: right shift per 8-bit R/G/B 0x5 - 0x7: Reserved 0: normal 1: flip msbs to lsbs 0: normal 1: swap R and B data 0: in 1 ppc, A channel active 0: in 2 ppc, Left on A, Right on B 1: in 1 ppc, B channel active 1: 2ppc, Left on B, Right on A 0: single wide, one pix/clk (ppc) 1: double wide, two pix/clk Vsync Output Polarity Hsync Output Polarity Data Enable Output Polarity Clock Output Invert Data Invert Output Polarity Data Invert Enable 0: TCON outputs set to zero 1: TCON outputs active 0: all data outputs set to zero 1: output enabled
R/W R/W R/W R/W
[6:4] [3] [2] [1]
0x0 0x0 0x0 0x0
R/W OMUX_CTRL_1 0x0C31 R/W R/W R/W R/W R/W R/W R/W R/W
[0] [7] [6] [5] [4] [3] [2] [1] [0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
77/89
Output Multiplexer
Table 32: Output Mux Registers (Sheet 2 of 4) Register Name
OMUX_CTRL_2
ADE3700
Addr
0x0C32
Mode
R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7] [6] [5] [4] [3] [2] [1] [0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Separate TCON driven invert enable TCON driven invert pin enable RSDS enable Per Pin Delay Enable Resync on Vsync Falling Edge Resync on Vsync Rising Edge Resync on Hsync Falling Edge Resync on Hsync Rising Edge Delay for OBA1 Delay for OBA0 Delay for OBA3 Delay for OBA2 Delay for OBA5 Delay for OBA4 Delay for OBA7 Delay for OBA6 Delay for OGA1 Delay for OGA0 Delay for OGA3 Delay for OGA2 Delay for OGA5 Delay for OGA4 Delay for OGA7 Delay for OGA6 Delay for ORA1 Delay for ORA0 Delay for ORA3 Delay for ORA2 Delay for ORA5 Delay for ORA4 Delay for ORA7 Delay for ORA6 Delay for OBB1 Delay for OBB0
OMUX_DLY_BA0
0x0C50
R/W R/W
OMUX_ DLY_BA2
0x0C4F
R/W R/W
OMUX_ DLY_BA4
0x0C4E
R/W R/W
OMUX_ DLY_BA6
0x0C4D
R/W R/W
OMUX_ DLY_GA0
0x0C4C
R/W R/W
OMUX_ DLY_GA2
0x0C4B
R/W R/W
OMUX_ DLY_GA4
0x0C4A
R/W R/W
OMUX_ DLY_GA6
0x0C49
R/W R/W
OMUX_ DLY_RA0
0x0C48
R/W R/W
OMUX_ DLY_RA2
0x0C47
R/W R/W
OMUX_ DLY_RA4
0x0C46
R/W R/W
OMUX_ DLY_RA6
0x0C45
R/W R/W
OMUX_ DLY_BB0
0x0C44
R/W R/W
78/89
ADE3700
Table 32: Output Mux Registers (Sheet 3 of 4) Register Name
OMUX_ DLY_BB2
Output Multiplexer
Addr
0x0C43
Mode
R/W R/W
Bits
[7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Delay for OBB3 Delay for OBB2 Delay for OBB5 Delay for OBB4 Delay for OBB7 Delay for OBB6 Delay for ORB1 Delay for ORB0 Delay for ORB3 Delay for ORB2 Delay for ORB5 Delay for ORB4 Delay for ORB7 Delay for ORB6 Delay for ORB1 Delay for ORB0 Delay for ORB3 Delay for ORB2 Delay for ORB5 Delay for ORB4 Delay for ORB7 Delay for ORB6 Delay for TCON1 Delay for TCON0 Delay for TCON3 Delay for TCON2 Delay for TCON5 Delay for TCON4 Delay for TCON7 Delay for TCON6 Delay for VSYNC Delay for ENAB Delay for CLK Delay for HSYNC
OMUX_ DLY_BB4
0x0C42
R/W R/W
OMUX_ DLY_BB6
0x0C41
R/W R/W
OMUX_ DLY_GB0
0x0C40
R/W R/W
OMUX_ DLY_GB2
0x0C3F
R/W R/W
OMUX_ DLY_GB4
0x0C3E
R/W R/W
OMUX_ DLY_GB6
0x0C3D
R/W R/W
OMUX_ DLY_RB0
0x0C3C
R/W R/W
OMUX_ DLY_RB2
0x0C3B
R/W R/W
OMUX_ DLY_R_B4
0x0C3A
R/W R/W
OMUX_ DLY_R_B6
0x0C39
R/W R/W
OMUX_ DLY_TCON_0
0x0C38
R/W R/W
OMUX_ DLY_TCON_2
0x0C37
R/W R/W
OMUX_ DLY_TCON_4
0x0C36
R/W R/W
OMUX_ DLY_TCON_6
0x0C35
R/W R/W
OMUX_ DLY_VS_ENAB
0x0C34
R/W R/W
OMUX_ DLY_CLK_HS
0x0C33
R/W R/W
79/89
Pulse Width Modulation (PWM)
Table 32: Output Mux Registers (Sheet 4 of 4) Register Name
OMUX_CTRL_3
ADE3700
Addr
0x0C51
Mode
R/W R/W R/W R/W
Bits
[7:3] [2] [1] [0] [7:6]
Default
Reserved 0x0 0x0 0x0
Description
PWM mux mode PWM enable TCON data invert enable, with computed data invert pin. Reserved
OMUX_REFCOUNT
0x0C52 R
[5:0]
0x0
Returns a value that indicates the ADE gate speed -- a function of temp and voltage higher = faster logic
2.20
Pulse Width Modulation (PWM)
The PWM block generates two signals that can be used to control backlight inverter switching power components directly. It is derived from XCLK and can be powered up independently of the DOTCLK and INCLK domains. The frequency, duty cycle, polarity and overlap/non-overlap are programmable. The output frequency can be free-running or locked to the output vsync signal.
Table 33: PWM Registers (Sheet 1 of 2) Register Name Addr
0x01A0
Mode
R
Bits
[7]
Default
0x0 PWM status 0: unlocked 1: locked
Description
PWM_CTRL0
R/W
[6]
0x0
0: lock to CYCLES_PER_FRAME from the free-running state machine 1: lock to CYCLES_PER_FRAME register setting PWM_A polarity 0: active low 1: active high
R/W
[5]
0x0
R/W
[4]
0x0
PWM_B polarity 0: active low 1: active high
R/W R/W
[3] [2]
0x0 0x0
0: normal operation 1: force PWM outputs to polarity settings 0: change period or duty cycle at the end of the current cycle 1: smooth change, period or duty cycle increment/decrement every PWM_STEP_DELAY cycle 0: free-running 1: lock to out_vsync 0: disable PWM output 1: enable PWM output
R/W R/W
[1] [0]
0x0 0x0
80/89
ADE3700
Table 33: PWM Registers (Sheet 2 of 2) Register Name
PWM_CTRL1
DFT Block
Addr
0x01A1
Mode
R/W
Bits
[7:4]
Default
0x0
Description
Lock 2nd order gain (power of 2) 0x0 = max 0x3 = typical 0xF = min.
R/W
[3:0]
0x0
Lock gain (power of 2) 0x0 = max 0x6 = typical 0xF = min. Period-2 in free-running mode, in XCLKs
PWM_PERIOD_L PWM_PERIOD_H PWM_DUTY_L PWM_DUTY_H PWM_OVERLAP_L PWM_OVERLAP_H PWM_STEP_DELAY
0x01A2 0x01A3 0x01A4 0x01A5 0x01A6 0x01A7 0x01A8
R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0
0x0
Duty cycle of PWM in XCLKs
0x0
Non-overlap of PWMs in XCLKs
0x0
In smooth change mode, the number of cycles skipped before the period/duty registers are incremented/decremented The number of cycles per frame in frame lock mode when not using the internally generated cycles per frame from a previous free-running mode
PWM_CYCLES_PER_FRAME_L PWM_CYCLES_PER_FRAME_H
0x01A9 0x01AA
R/W R/W
[7:0] [7:0]
0x0
2.21
DFT Block
Table 34: DFT Registers (Sheet 1 of 3) Register Name Addr
0x0F00 R/W R/W R/W R/W
Mode
Bits
[7:4] [3] [2] [1] [0] [7:6]
Default
Reserved 0x0 0x0 0x0 0x0
Description
DFT_TEST_MODE
trigger video bus MFSR enable output pin MFSR clear output pin MFSR output pin test override Reserved
DFT_MUX_OUT_MODE
0x0F01 R/W
[5:0] [7:6]
0x0
mux selector for output porta/b and syncs Reserved
DFT_FLOP_OUT_MODE
0x0F02 R/W
[5:0] [7:6]
0x0 0x0
mux selector for synchronous digital debug bus divide-by selector for clocks to OCLK pin fout = selected clock / (2 ^ value)
DFT_CLK_0UT_MODE
0x0F03
R/W
R/W DFT_CLK_1_MODE 0x0F04 R/W
[5:0] [7:6]
0x0 0x0
mux selector for clocks to OCLK pin divide-by selector for clocks to CLKOUT pin fout = selected clock / (2 ^ value)
81/89
DFT Block
Table 34: DFT Registers (Sheet 2 of 3) Register Name
DFT_CLK_2_MODE DFT_OUT_DISAB_0 DFT_OUT_DISAB_1 DFT_OUT_DISAB_2 DFT_OUT_DISAB_3 DFT_OUT_DISAB_4 DFT_OUT_DISAB_5 DFT_OUT_DISAB_6
ADE3700
Addr
0x0F05 0x0F06 0x0F07 0x0F08 0x0F09 0x0F0A 0x0F0B 0x0F0C
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[5:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3] [2] [1] [0] [7:5]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
mux selector for clocks to CLKOUT pin Disable Port A Red Output in Test Mode Disable Port A Green Output in Test Mode Disable Port A Blue Output in Test Mode Disable Port B Red Output in Test Mode Disable Port B Green Output in Test Mode Disable Port B Blue Output in Test Mode Disable TCON Bits [4:0] in Test Mode Disable Vert Sync Output in Test Mode Disable Data Enab Output in Test Mode Disable Horz Sync Output in Test Mode Reserved
DFT_OUT_DISAB_7
0x0F0D R/W R/W R/W
[4] [3] [2:0] [7:6]
0x0 0x0 0x0
Disable CLKOUT Output In Test Mode Disable OCLK Output in Test Mode Disable TCON Bits [7:5] in Test Mode Reserved
DFT_STIM_CTRL
0x0F0E R/W
[0] [7] [6:2] [1] [0] [7:6]
0x0 0x0
Internal Stimulus Bus Enable SCL Test Stimulus Enable Reserved
DFT_STIM_EN_0
0x0F0F
R/W R/W R/W R/W
0x0 0x0
ADC Test Stimulus Enable NC Reserved
DFT_STIM_EN_1
0x0F10 R/W R/W R/W R/W R/W R/W
[5] [4] [3] [2] [1] [0] [7:6]
0x0 0x0 0x0 0x0 0x0 0x0
TCON test bypass OMUX test stimulus enable APC test stimulus enable OSD test stimulus enable SCL bypass PGEN test stimulus enable Reserved Gamma RAM BIST end OSD CS RAM BIST end OSD DRB RAM BIST OSD MB RAM BIST end SCL coeff. RAM BIST end SCL line buffer RAM BIST end
DFT_BIST_STATUS
0x0F11 R R R R R R
[5] [4] [3] [2] [1] [0]
82/89
ADE3700
Table 34: DFT Registers (Sheet 3 of 3) Register Name
DFT_BIST_RESULT_0
IC RAM Addresses
Addr
0x0F12
Mode
Bits
[7:6]
Default
Reserved
Description
R R R R R R DFT_BIST_RESULT_1 0x0F13 R R R R R R R DFT_MFSR_DONE 0x0F14 R DFT_MFSR_SIG_0 DFT_MFSR_SIG_1 DFT_MFSR_SIG_2 DFT_MFSR_SIG_3 0x0F15 0x0F16 0x0F17 0x0F18 R R R R
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7:1] [0] [7:0] [7:0] [7:0] [7:0] 0x0
SCL coeff RAM 2 BIST fail SCL coeff RAM 1 BIST fail SCL line buffer 4 BIST fail SCL line buffer 3 BIST fail SCL line buffer 2 BIST fail SCL line buffer 1 BIST fail Reserved Gamma blue RAM BIST fail Gamma green RAM BIST fail Gamma red RAM BIST fail OSD CS RAM1 BIST fail OSD CS RAM 2 BIST fail OSD DRB RAM BIST fail OSD MB RAM BIST fail Reserved done signal video bus MFSR
2.22
IC RAM Addresses
Table 35: IC RAM Addresses Name
GAM_RED GAM_GREEN GAM_BLUE OSD_MB OSD_CS OSD_DRB SCL_COEFF SCL_LINE1 SCL_LINE2 SCL_LINE3 SCL_LINE4
Start Addr
0x1000 0x1200 0x1400 0x1700 0x3000 0x6000 0x9000 0x9900 0xA800 0xB700 0xC600
End Addr
11FF 13FF 15FF 175F 5F3F 647F 98FF A7FF B6FF C5FF D4FF
Description
Gamma LUT, Red, LSB0,MSB0,LSB1,... (256x10) Gamma LUT, Green, (256x10) Gamma LUT, Blue, (256x10) OSD Color LUTs (32x24) OSD Character Map (1344x36x2 copies) OSD Screen Map (1152x8) Scaler coefficient RAM (256x36x2 copies) Scaler line buffer 1 (1280x24) Scaler line buffer 2 (1280x24) Scaler line buffer 3 (1280x24) Scaler line buffer 4 (1280x24)
83/89
Absolute Maximum Ratings
ADE3700
3
3.1
Electrical Specifications
Absolute Maximum Ratings
Symbol Parameter
Supply voltage
Min.
Typ.
Max.
1.95
Unit
V
AVDD18 DVDD18 XVDD18 LVDD18 AVDD33 DVDD33 VIN TSTG
Supply voltage Max voltage on 5 volt tolerant input pins Storage temperature -40
3.6 6.1 +150
V V C
3.2
Power Consumption Matrices
Table 36: ADE3700x
Symbol
Parameter
Supply Current (Analog Input, XGA@75Hz, 78.75MHz)
Min
Typ*
Max**
Unit
IAVDD18 IDVDD18 IAVDD33 IDVDD33 PTOTANA
1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Total Power Consumption (Analog Input, XGA@75Hz, 78.75MHz)
195 228 102 44 1.25
203 257 105 51 1.48
mA mA mA mA W
* **
Measured at nominal voltage supplies Measured at +10% voltage supplies
Table 37: ADE3700xs
Symbol
Parameter
Supply Current (Analog Input, XGA@75Hz, 135MHz)
Min
Typ*
Max**
Unit
IAVDD18 IDVDD18 IAVDD33 IDVDD33 PTOTANA
1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Total Power Consumption (Analog Input, XGA@75Hz, 135MHz)
200 351 104 68 1.56
207 401 108 80 1.89
mA mA mA mA W
* **
Measured at nominal voltage supplies Measured at +10% voltage supplies
84/89
ADE3700
Nominal Operating Conditions
3.3
Nominal Operating Conditions
Symbol Parameter
Supply Voltage
Min.
1.71
Typ.
1.8
Max.
1.89
Unit
V
AVDD18 DVDD18 XVDD18 LVDD18 AVDD33 DVDD33 fXTAL TOPER
Supply Voltage Crystal Frequency Ambient Operating Temperature
3.135
3.3 27
3.465
V MHz
0
+70
C
3.4
Preliminary Thermal Data
Parameter
Junction-to-Ambient Thermal Resistance, 144-pin package Junction-to-Ambient Thermal Resistance, 128-pin package
Symbol
RthJA RthJA
Min.
Typ.
Max.
25 35
Unit
C/W C/W
3.5
Preliminary DC Specifications
Test Conditions: DVDD33 = AVDD33 = 3.3V, DVDD18 = AVDD18 = XVDD18 = LVDD18 = 1.8V and TAMB = 25C
3.5.1
LVTTL 5 Volt Tolerant Inputs With Hysteresis
YUV[0:7], YUVCLK, HSYNC, VSYNC, CSYNC, TCON_IN, SCL, RESETN
Symbol
VIH VIL VHYST
Parameter
High Level Input Voltage Low Level Input Voltage Schmitt Trigger Hysteresis
Condition
Min.
2.0
Typ.
Max.
Unit
V
0.8 0.4
V V
3.5.2
LVTTL 5 Volt Tolerant Inputs
XCLK_EN
Symbol
VIH VIL
Parameter
High Level Input Voltage Low Level Input Voltage
Condition
Min.
2.0
Typ.
Max.
Unit
V
0.8
V
85/89
Preliminary AC Specifications 3.5.3 LVTTL 5 Volt Tolerant I/O With Hysteresis
SDA
Symbol
VIH VIL VHYST
ADE3700
Parameter
High Level Input Voltage Low Level Input Voltage Schmitt Trigger Hysteresis
Condition
Min.
2.0
Typ.
Max.
Unit
V
0.8 0.4
V V
3.5.4
LVTTL Outputs
OBA[0:7], OGA[0:7], ORA[0:7], OBB[0:7], OGB[0:7], ORB[0:7], OHS, OVS, ODE, OCLK
Symbol
VIH VIL IIH IIL
Parameter
High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current
Condition
Min.
2.0
Typ.
Max.
Unit
V
0.8 VIN = VDD VIN = 0V -10 10
V A A
3.6
Preliminary AC Specifications
Parameter
RSDS Differential Output Voltage RSDS Common Mode Output Voltage RSDS Transition Time To 90% ADC Integral Nonlinearity (9-bit) ADC Differential Nonlinearity (9-bit) ADC Input Voltage Range ADC Effective Number Of Bits 135 MSPS Input = 65 MHz sine at 95% FS no missing codes 0.5 7.5 200 8 20 0.05 4 0.1 140
Symbol
Vrsds_diff Vrsrs_cm Trise, Tfall INL DNL Vadc_in ENOB
Condition
RSDS mode 680 ohm + 50 ohm external termination to 1.3V CL = 30pF
Min.
100 1.1
Typ.
200 1.3
Max.
400 1.5 3
Unit
mV V ns LSB LSB
1.5 1.5 1
Vp-p bits Kohms pF MHz dB mV uF
Radc_in Cadc_in Fadc ADC gain step ADC offset step Cadc_ext
ADC Input Resistance ADC Input Capacitance ADC Sample Frequency ADC Gain Step Size ADC Offset Step Size ADC External AC Coupling Cap
86/89
ADE3700
Preliminary AC Specifications
4
Package Mechanical Data
D D1 11/13 b
D2
E2 E1 e E
Pin 1 Identification A 0 Min.
0.08/0.20 R. A2
A1 0.08 R. Min. L L1
K 0.25 mm. Gauge Plane
Dimensions (mm) Min.
A A1 A2 b D D1 D2 E E1 E2 e L L1 K
Dimensions (inches) Max.
1.600 0.150 1.450 0.270
Typ.
Min.
Typ.
Max.
0.063 0.006 0.057 0.011
1.400 0.220 22.000 20.000 16.000 14.000 0.500 0.600 1.000
1.350 0.170
0.055 0.009 0.866 0.787 0.623 0.551 0.020 0.024 0.040
0.053 0.007
0.450 0.000
0.750 7.000
0.0178 0.000
0.030 0.275
87/89
Preliminary AC Specifications
ADE3700
5
Revision History
Table 38: Summary of Modifications Date Version
0.1 0.2 First Draft Addition of diagram on Cover. Modification of Description and Product Selector info on 1st page. Modification of Section 2.7.1: Functional Description (SMUX) and Table 11: Sync Multiplexer Registers. Modification of Table 7: Line Lock PLL Registers, Table 14: Data Measurement Registers, Table 15: LCD Scaler Registers and Table 24: Flicker Registers. Device named changed from ADE3700X to ADE3700. Modification of block diagram and table on cover. Modification of registers SMEAS_V_CTRL and GLBL_INCLK_GATE_CTRL Modification of package data (128-pin LQFP). Changes to Pin Description information. Update of Timing Controller information. Inclusion of Section 3.2: Power Consumption Matrices on page 84.
Description
12 August 2002 23 August 2002
17 October 2002 26 Nov 2002 4 Dec 2002 9 Jan 2003 10 July 2003
0.3 0.4 0.5 0.6 0.7
88/89
ADE3700
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
www.st.com
89/89
This datasheet has been download from: www..com Datasheets for electronics components.

▲Up To Search▲

Price & Availability of ADE3700SX

	To Download ADE3700SX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .